DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2011/0100457) in view of Moslehi et al. (US 2013/0167915).
Regarding claim 1, Kim discloses a charge storage structure in Figures 16-17 comprising:
a wafer (silicon substrate 310) comprising a first surface (front surface) and a second surface (back surface) opposite to the first surface ([45] and Figures 16-17),
wherein the first surface has a first texture (front surface has pyramidal texture, Figures 16-17 and [45]), and the second surface (back surface) comprises a first part with a second texture (portions between polar regions have the second texture) and a second part connected to the first part (portions where polar regions are located are the “second part”);
a first polar region (n-type region 330), configured to be in contact with the first part of the second surface (Figure 16 and [57]); and
a second polar region (p-type region 340), spaced apart from the first polar region (330) and configured to be adjacent to the second part of the second surface (Figure 16 and [57]),
wherein the first texture (front surface texture) is different from the second texture (Figures 16 and 17).
Kim additionally discloses that the second texture (portions between polar regions have the second texture) is a textured surface defining both an alkali polished shape and a pyramidal shape (As shown in Figures 16 and 17, [45]-[47], and [51]-[56], the laser processing to remove portions of the oxide layer results in portions between the doped regions of the substrate surface that are flat and read on “an alkali polished shape” and portions that have a pyramidal shape), and the second texture is disposed between the first polar region and the second polar region (portions between polar regions have the second texture as shown in Figures 16-17).
Kim does not explicitly disclose that the second texture is a micro-texture.
Moslehi discloses a back contact solar cell device (abstract) comprising a micro-texture comprising a pyramidal shape on the back surface ([73] and Figure 24).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Kim such that the second texture is a micro-texture surface, as taught by Moslehi, because the micro-texture provides light trapping effects which improves the efficiency of the device (Moslehi, [73]). Additionally, a change in size (dimension) is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955).
Regarding claim 2, modified Kim discloses all of the claim limitations as set forth above. Kim additionally discloses that the first texture is any one of a pyramidal texture or an inverted pyramidal texture ([45]).
Regarding claim 3, modified Kim discloses all of the claim limitations as set forth above. Kim additionally discloses that an oxide layer (323) covering the second part of the second surface of the wafer ([47]-[48]).
Regarding claim 4, modified Kim discloses all of the claim limitations as set forth above. Kim additionally discloses a semiconductor layer (layer 370 can be TiO2 which is a semiconductor material) covering the oxide layer (323) ([59] and Figure 17).
Regarding claim 10, modified Kim discloses all of the claim limitations as set forth above. Kim additionally discloses that the second polar region (340) comprises a second metal contact (390) connected to the semiconductor layer, and the second metal contact is connected to the semiconductor layer without passing through an opening (Figure 17 and [60]).
Claims 5-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2011/0100457) in view of Moslehi et al. (US 2013/0167915), as applied to claim 4 above, in further view of Scherff et al. (US 2009/0317934).
Regarding claim 5, Kim discloses all of the claim limitations as set forth above. Kim additionally discloses a first passivation (321, [47]-[48]), which covers the first surface (front surface in Figures 15 and 17). Kim does not disclose that the first passivation layer also covers the first part of the second surface, a third surface of the wafer located between the first surface and the second surface, a side surface of the oxide layer, and a side surface of the semiconductor layer.
Scherff discloses a semiconductor device in Figure 1 comprising a first passivation layer (21) on a first surface (top surface) of a wafer (1) which also covers a first part of a second surface (bottom surface) of the wafer (1) opposite the first surface, a third surface (side surface) of the wafer (1) located between the first surface and the second surface (Figure 1, [3]-[4], [36], [47], [123]-[124]).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Kim such that the first passivation layer also covers the first part of the second surface, a third surface of the wafer located between the first surface and the second surface, a side surface of the oxide layer, and a side surface of the semiconductor layer, as taught by Scherff, because it would amount to nothing more than the combination of prior art elements according to known methods to yield predictable results.
Regarding claim 6, modified Kim discloses all of the claim limitations as set forth above. Modified Kim additionally discloses a second passivation layer covering the first passivation layer (Scherff, [173]-[175] and [177], the passivation layer can be a stack of materials which includes a first and second passivation layer).
Regarding claim 7, modified Kim discloses all of the claim limitations as set forth above. Kim additionally discloses that the first polar region comprises a first metal contact (electrode 390) and a region connected to the first metal contact (Figures 10, 17 and [60]).
Regarding claim 9, modified Kim discloses all of the claim limitations as set forth above. Modified Kim additionally discloses that both the first passivation layer and the second passivation layer located on the first part of the second surface define a first opening, and the first metal contact (390) of the first polar region passes through the first opening (Figure 10 and [18], electrode passes through an opening in the passivation layers to reach the first polar region).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDSEY A BUCK whose telephone number is (571)270-1234. The examiner can normally be reached Monday-Friday 9am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Martin can be reached at (571)270-7871. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LINDSEY A BUCK/Primary Examiner, Art Unit 1728
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