DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 9-14 are objected to because of the following informalities:
As to claim 9, the phrase “a data signal terminal in at least a part” in line 2 of the claim should be changed to “the data signal terminal in at least the part”, since “data signal terminal in at least a part” was previously recited in claim 1. Appropriate correction is required.
As to claim 9, the phrase “a reference signal terminal” in line 3 of the claim should be changed to “the reference signal terminal”, since “ reference signal terminal” was previously recited in claim 1. Appropriate correction is required.
As to claim 10, the phrase “the fifth node” in line 7 of the claim should be changed to “ a fifth node”, since “a fifth node” was not previously recited in the claim. Appropriate correction is required.
As to claim 11, the phrase “the third scan signal terminal ” in line 1 of the claim should be changed to “ a third scan signal terminal”, since “a third scan signal terminal” was not previously recited in the claim. Appropriate correction is required.
As to claim 12, the phrase “a data signal terminal” in line 2 of the claim should be changed to “the data signal terminal”, since “data signal terminal” was previously recited in claim 1. Appropriate correction is required.
As to claim 12, the phrase “a reference signal terminal” in lines 2-3 of the claim should be changed to “the reference signal terminal”, since “ reference signal terminal” was previously recited in claim 1. Appropriate correction is required.
As to claim 13, the phrase “the fifth node” in line 8 of the claim should be changed to “ a fifth node”, since “a fifth node” was not previously recited in the claim. Appropriate correction is required.
As to claim 14, the phrase “the third scan signal terminal ” in line 1 of the claim should be changed to “ a third scan signal terminal”, since “a third scan signal terminal” was not previously recited in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 8-14, 17 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (CN 116229896 A, cited in the Information Disclosure Statement (IDS), English machine translation filed on 03/12/2025 is used in the rejection).
As to claim 1, Cheng teaches a pixel driving circuit ([0004]: pixel), comprising: a first node control sub-circuit (transistor M4, transistor M7 and capacitor C2 in Fig. 2), a second node control sub-circuit (transistors M1, M2, M3, M5, capacitors C1 and C3 in Fig. 2) and a driving sub-circuit (transistor M1 in Fig. 2);
wherein the driving sub-circuit (transistor M1 in Fig. 2) is electrically connected to a first node (node N1 in Fig. 2), a second node (node directly connecting transistor M1 and M6 in Fig. 2), and a third node respectively (node N2 in Fig. 2), and is configured to provide a driving signal to the second node under control of signals of the first node (node N1 in Fig. 2) and the third node (node N2 in Fig. 2;[0104-0106]: light-emitting stage, transistor M1 connected to power supply terminal VDD and drives light emitting element D to emit light, Fig. 2);
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the first node control sub-circuit (transistor M4, transistor M7 and capacitor C2 in Fig. 2) is
electrically connected to a first scan signal terminal (S1n signal terminal in Fig. 2), a second scan signal
terminal (S3n signal terminal in Fig. 2), a first initial signal terminal (Vini signal terminal in Fig. 2), the first
node (node N1 in Fig. 2) and the second node, respectively (node directly connecting transistor M1 and
M6 in Fig. 2), and is configured to provide a signal of the first initial signal terminal to the first node
([0096]: transistor M4 is turned on, voltage of the first node N1 is set to the reset voltage Vini) under
control of signals of the first scan signal terminal (S1n signal terminal in Fig. 2;[0096]) and the second
scan signal terminal (S3n signal terminal in Fig. 2;[0045]: Figure 3 is the driving timing diagram of the
pixel circuit; [0095];[0099]: power supply terminal VDD charges the voltage of the first node N1 in
sequence through the fifth transistor M5, the first transistor M1 and the seventh transistor M7;[0105]:
when signal S3n is invalid, transistor M7 is turned off), and change a signal of the first node by a signal of
the second node ([0045];[0099]: power supply terminal VDD charges the voltage of the first node N1 in
sequence through the fifth transistor M5, the first transistor M1 and the seventh transistor M7. Fig. 2
shows transistor M7 connected between node N1 (i.e. first node) and node directly connecting
transistor M1 and M6 (I.e. second node); [0105]: when signal S3n is invalid, transistor M7 is turned off);
the second node control sub-circuit (transistors M1, M2, M3, M5, capacitors C1 and C3 in Fig. 2)
is electrically connected to at least one scan signal terminal (En1 signal terminal in Fig. 2), the second
node (node directly connecting transistor M1 and M6 in Fig. 2), a voltage stabilizing signal terminal (S5n
signal terminal in Fig. 2) and a writing signal terminal respectively (VDD signal terminal in Fig. 2), and is
configured to change the signal of the second node (node directly connecting transistor M1 and M6 in
Fig. 2) by a signal of the writing signal terminal (VDD signal terminal in Fig. 2; [0104-0105]: light-emitting
stage, transistor M1 connected to power supply terminal VDD, drive light emitting element D to emit
light, Fig. 2) under control of signals of the at least one scan signal terminal (En1 signal terminal in Fig. 2;
[0104-0105]: signal En1 is active, the fifth transistor M5 is turned on) and the voltage stabilizing signal
terminal (S5n signal terminal in Fig. 2;[0045];[0099]: stage t2, signal S5n is valid, transistor M3 is turned
on, and transistor M1 is turned on);
the writing signal terminal comprises a data signal terminal (Vdata signal terminal in Fig. 2) and a reference signal terminal (VDD terminal in Fig. 2), or the writing signal terminal is a data signal terminal in at least a part of a time period ([0074]: transistor M2 receives the data voltage Vdata; [0101-0102]: control signal S4n is active, transistor M2 is turned on. Phase t3, voltage of node N3 jumps to data voltage Vdata, Fig. 3) and is a reference signal terminal in at least another part of a time period ([0102]: stage t2, voltage of node N3 is the voltage of power supply terminal VDD;[0104-0105]: stage t4, transistor M5 connected to power supply terminal VDD is turned on);
the first node control sub-circuit comprises at least one capacitor (capacitor C2 in Fig. 2), the second node control sub-circuit comprises at least two capacitors (capacitors C1 and C3 in Fig. 2) and at least one transistor (transistor M2 in Fig. 2), and the at least one capacitor in the first node control sub-circuit (capacitor C2 in Fig. 2) is electrically connected to the at least one transistor in the second node control sub-circuit (transistor M2 in Fig. 2) by at least one capacitor in the second node control sub-circuit (capacitor C1 in Fig. 2).
As to claim 3, Cheng teaches the pixel driving circuit of claim 1, wherein the first node control sub-circuit comprises a node reset sub-circuit (transistor M4 in Fig. 2) and a node compensation sub-circuit (transistor M7 in Fig. 2);
the node reset sub-circuit (M4 in Fig. 2) is electrically connected to the first scan signal terminal (S1n signal terminal in Fig. 2), the first initial signal terminal (Vini signal terminal in Fig. 2) and the first node respectively (node N1 in Fig. 2), and is configured to provide a signal of the first initial signal terminal (Vini signal terminal in Fig. 2)to the first node (node N1 in Fig. 2) under control of a signal of the first scan signal terminal (S1n signal terminal in Fig. 2;[0096]: transistor M4 is turned on, voltage of the first node N1 is set to the reset voltage Vini); and
the node compensation sub-circuit (transistor M7 in Fig. 2) is electrically connected to the first node (node N1 in Fig. 2), the second node (node directly connecting transistor M1 and M6 in Fig. 2), and the second scan signal terminal respectively (S3n signal terminal in Fig. 2), and is configured to change the signal of the first node (node N1 in Fig. 2) by the signal of the second node under control of the signal of the second scan signal terminal (S3n signal terminal in Fig. 2;[0045];[0095];[0099]: power supply terminal VDD charges the voltage of the first node N1 in sequence through the fifth transistor M5, the first transistor M1 and the seventh transistor M7;[0105]: when signal S3n is invalid, transistor M7 is turned off).
As to claim 4, Cheng teaches the pixel driving circuit of claim 3, wherein the node reset sub-circuit comprises a first transistor (transistor M4 in Fig. 2);
a control electrode of the first transistor (transistor M4 in Fig. 2) is electrically connected to the first scan signal terminal (S1n signal terminal in Fig. 2), a first electrode of the first transistor (transistor M4 in Fig. 2) is electrically connected to the first initial signal terminal (Vini signal terminal in Fig. 2), and a second electrode of the first transistor (transistor M4 in Fig. 2) is electrically connected to the first node (node N1 in Fig. 2).
As to claim 5, Cheng teaches the pixel driving circuit of claim 3, wherein the node compensation sub-circuit comprises a first capacitor (capacitor C2 in Fig. 2) and a second transistor (transistor M7 in Fig. 2),
one terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to the first node (node N1 in Fig. 2), and the other terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to a first electrode of the second transistor (transistor M7 in Fig. 2: note that the claim does not recite “directly” connected. All of the elements in Fig. 2 of Cheng are connected to each other); and
a control electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the second scan signal terminal (S3n signal terminal in Fig. 2), and a second electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2); or wherein the node compensation sub-circuit comprises a first capacitor (capacitor C2 in Fig. 2) and a second transistor (transistor M7 in Fig. 2); one terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2), and the other terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to a second electrode of the second transistor (transistor M7 in Fig. 2); and a control electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the second scan signal terminal (S3n signal terminal in Fig. 2), and a first electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the first node (node N1 in Fig. 2); or wherein the node compensation sub-circuit comprises a first capacitor, a second transistor, and a fourth capacitor;
one terminal of the first capacitor is electrically connected to the first node, and the other terminal of the first capacitor is electrically connected to a first electrode of the second transistor; one terminal of the fourth capacitor is electrically connected to the second node, and the other terminal of the fourth capacitor is electrically connected to a second electrode of the second transistor; and a control electrode of the second transistor is electrically connected to the second scan signal terminal (note the word “or” recited in the claim. Cheng teaches wherein the node compensation sub-circuit comprises a first capacitor (capacitor C2 in Fig. 2) and a second transistor (transistor M7 in Fig. 2), one terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to the first node (node N1 in Fig. 2), and the other terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to a first electrode of the second transistor (transistor M7 in Fig. 2: note that the claim does not recite “directly” connected. All of the elements in Fig. 2 of Cheng are connected to each other); and a control electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the second scan signal terminal (S3n signal terminal in Fig. 2), and a second electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2); or wherein the node compensation sub-circuit comprises a first capacitor (capacitor C2 in Fig. 2) and a second transistor (transistor M7 in Fig. 2); one terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2), and the other terminal of the first capacitor (capacitor C2 in Fig. 2) is electrically connected to a second electrode of the second transistor (transistor M7 in Fig. 2); and a control electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the second scan signal terminal (S3n signal terminal in Fig. 2), and a first electrode of the second transistor (transistor M7 in Fig. 2) is electrically connected to the first node (node N1 in Fig. 2)).
As to claim 8, Cheng teaches the pixel driving circuit of claim 3, wherein the first scan signal terminal (S1n signal terminal in Fig. 2) and the second scan signal terminal (S3n signal terminal in Fig. 2) are different signal terminals or are a same signal terminal (S1n signal terminal and S3n signal terminal in Fig. 2 are different signal terminals).
As to claim 9, Cheng teaches the pixel driving circuit of claim 1, wherein when the writing signal terminal is a data signal terminal in at least a part of the time period ([0074]: transistor M2 receives the data voltage Vdata; [0101-0102]: control signal S4n is active, transistor M2 is turned on. Phase t3, voltage of node N3 jumps to data voltage Vdata, Fig. 3) and a reference signal terminal in at least another part of the time period ([0102]: stage t2, voltage of node N3 is the voltage of power supply terminal VDD;[0104-0105]: stage t4, transistor M5 connected to power supply terminal VDD is turned on), the at least one scan signal terminal comprises a fourth scan signal terminal (En1 signal terminal in Fig. 2), and the second node control sub-circuit (transistors M1, M2, M3, M5, capacitors C1 and C3 in Fig. 2) is respectively connected to the fourth scan signal terminal (En1 signal terminal in Fig. 2; note that the claim does not recite “directly” connected. All of the elements in Fig. 2 of Cheng are connected to each other), the second node (node directly connecting transistor M1 and M6 in Fig. 2), the voltage stabilizing signal terminal (S5n signal terminal in Fig. 2) and the writing signal terminal (VDD signal terminal in Fig. 2).
As to claim 10, Cheng teaches the pixel driving circuit of claim 9, wherein the second node control sub-circuit comprises a second capacitor (capacitor C1 in Fig. 2), a third capacitor (capacitor C3 in Fig. 2), a fourth transistor (transistor M5 in Fig. 2);
one terminal of the second capacitor (capacitor C1 in Fig. 2) is electrically connected to the voltage stabilizing signal terminal (S5n signal terminal in Fig. 2; note that the claim does not recite “directly” connected. All of the elements in Fig. 2 of Cheng are connected to each other), and the other terminal of the second capacitor (capacitor C1 in Fig. 2), is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2);
one terminal of the third capacitor (capacitor C3 in Fig. 2) is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2), and the other terminal of the third capacitor (capacitor C3 in Fig. 2) is electrically connected to the fifth node (node directly connecting capacitors C2 and C3 in Fig. 2);
a control electrode of the fourth transistor (transistor M5 in Fig. 2) is electrically connected to the fourth scan signal terminal (En1 signal terminal in Fig. 2), a first electrode of the fourth transistor (transistor M5 in Fig. 2) is electrically connected to the writing signal terminal (VDD terminal in Fig. 2), and a second electrode of the fourth transistor (transistor M5 in Fig. 2) is electrically connected to the fifth node(node directly connecting capacitors C2 and C3 in Fig. 2; note that the claim does not recite “directly” connected. All of the elements in Fig. 2 of Cheng are connected to each other).
As to claim 11, Cheng teaches the pixel driving circuit of claim 9, wherein the third scan signal terminal (S4n signal terminal in Fig. 2) and the fourth scan signal terminal (En1 signal terminal in Fig. 2) are different signal terminals (Fig. 2 shows S4n signal terminal, and En1 signal terminal in Fig. 2 are different signal terminals).
As to claim 12, Cheng teaches the pixel driving circuit of claim 1, wherein when the writing signal terminal comprises a data signal terminal (Vdata signal terminal in Fig. 2) and a reference signal terminal (VDD terminal in Fig. 2), the at least one scan signal terminal comprises a fourth scan signal terminal (En1 signal terminal in Fig. 2) and a fifth scan signal terminal (S4n signal terminal in Fig. 2), and the second node control sub-circuit (transistors M1, M2, M3, M5, capacitors C1 and C3 in Fig. 2) is electrically connected to the fourth scan signal terminal (En1 signal terminal in Fig. 2), the fifth scan signal terminal (S4n signal terminal in Fig. 2), the second node (node directly connecting transistor M1 and M6 in Fig. 2), the voltage stabilizing signal terminal (S5n signal terminal in Fig. 2), the reference signal terminal (VDD terminal in Fig. 2) and the data signal terminal, respectively (Vdata signal terminal in Fig. 2).
As to claim 13, Cheng teaches the pixel driving circuit of claim 12, wherein the second node control sub-circuit comprises a second capacitor (capacitor C1 in Fig. 2), a third capacitor (capacitor C3 in Fig. 2), a fourth transistor (transistor M5 in Fig. 2), and an eighth transistor (transistor M2 in Fig. 2);
one terminal of the second capacitor (capacitor C1 in Fig. 2) is electrically connected to the voltage stabilizing signal terminal (S5n signal terminal in Fig. 2; note that the claim does not recite “directly” connected. All of the elements in Fig. 2 are connected to each other), and the other terminal of the second capacitor (capacitor C1 in Fig. 2), is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2);
one terminal of the third capacitor (capacitor C3 in Fig. 2) is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2), and the other terminal of the third capacitor (capacitor C3 in Fig. 2) is electrically connected to the fifth node (node directly connecting capacitors C2 and C3 in Fig. 2);
a control electrode of the fourth transistor (transistor M5 in Fig. 2) is electrically connected to the fourth scan signal terminal (En1 signal terminal in Fig. 2), a first electrode of the fourth transistor (transistor M5 in Fig. 2) is electrically connected to the reference signal terminal (VDD terminal in Fig. 2), and a second electrode of the fourth transistor (transistor M5 in Fig. 2) is electrically connected to the fifth node(node directly connecting capacitors C2 and C3 in Fig. 2; note that the claim does not recite “directly” connected. All of the elements in Fig. 2 of Cheng are connected to each other); and
a control electrode of the eighth transistor (transistor M2 in Fig. 2) is electrically connected to the fifth scan signal terminal (S4n signal terminal in Fig. 2), a first electrode of the eighth transistor (transistor M2 in Fig. 2) is electrically connected to the data signal terminal (Vdata signal terminal in Fig. 2), and a second electrode of the eighth transistor (transistor M2 in Fig. 2) is electrically connected to the fifth node (node directly connecting capacitors C2 and C3 in Fig. 2).
As to claim 14, Cheng teaches the pixel driving circuit of claim 13, wherein the third scan signal terminal (S6n signal terminal in Fig. 2), the fourth scan signal terminal (En1 signal terminal in Fig. 2), and the fifth scan signal terminal (S4n signal terminal in Fig. 2) are different signal terminals (Fig. 2 shows S6n signal terminal, En1 signal terminal, and S4n signal terminal in Fig. 2 are different signal terminals).
As to claim 17, Cheng teaches a display apparatus ([0001]: display device), comprising the pixel driving circuit of claim 1 (see rejection for claim 1).
As to claim 27, Cheng teaches a driving method for a pixel driving circuit ([0001]: pixel circuit and its driving method), configured to drive the pixel driving circuit according to claim 1 (see rejection for claim 1), the method comprising:
providing, by the first node control sub-circuit, the signal of the first initial signal terminal to the first node ([0096]: transistor M4 is turned on, voltage of the first node N1 is set to the reset voltage Vini) under control of signals of the first scan signal terminal (S1n signal terminal in Fig. 2) and the second scan signal terminal (S3n signal terminal in Fig. 2;[0045]: Figure 3 is the driving timing diagram of the pixel circuit;[0095];[0099]: power supply terminal VDD charges the voltage of the first node N1 in sequence through the fifth transistor M5, the first transistor M1 and the seventh transistor M7;[0105]: when signal S3n is invalid, transistor M7 is turned off), and changing the signal of the first node by the signal of the second node ([0045];[0099]: power supply terminal VDD charges the voltage of the first node N1 in sequence through the fifth transistor M5, the first transistor M1 and the seventh transistor M7;[0105]: when signal S3n is invalid, transistor M7 is turned off);
changing, by the second node control sub-circuit, the signal of the second node (node directly connecting transistor M1 and M6 in Fig. 2) by the signal of the writing signal terminal (VDD signal terminal in Fig. 2; [0104]: light-emitting stage, transistor M1 connected to power supply terminal VDD, drive light emitting element D to emit light, Fig. 2) under the control of the signal of the at least one scan signal termina (En1 signal terminal in Fig. 2;[0104-0105]: signal En1 is active, the fifth transistor M5 is turned on);
providing, by the driving sub-circuit, the driving signal to the second node (node directly connecting transistor M1 and M6 in Fig. 2) under the control of the signals of the first node (node N1 in Fig. 2) and the third node (node N2 in Fig. 2;[0104]: light-emitting stage, transistor M1 connected to power supply terminal VDD, drive light emitting element D to emit light, Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (CN 116229896 A, cited in the Information Disclosure Statement (IDS), English machine translation filed on 03/12/2025 is used in the rejection) in view of Gao et al. (CN 116825035, cited in the Information Disclosure Statement (IDS), English machine translation filed on 03/12/2025 is used in the rejection).
As to claim 2, Cheng teaches the pixel driving circuit of claim 1, further comprising an anode reset sub-circuit (transistor M8 in Fig. 2) and a light emitting control sub-circuit (transistors M5 and M6 in Fig. 2);
wherein the anode reset sub-circuit (transistor M8 in Fig. 2) is electrically connected to a third scan signal terminal (S2n signal terminal in Fig. 2), initial signal terminal (Vini signal terminal in Fig. 2) and a fourth node respectively (node directly connecting transistor M6 and light emitting element D in Fig. 2), and is configured to provide a signal of the initial signal terminal to the fourth node under control of a signal of the third scan signal terminal ([0088-0089]: control electrode of the eighth transistor M8 receives the second control signal S2n, the first electrode of the eighth transistor M8 receives the reset voltage Vini, and the second electrode of the eighth transistor M8 is connected to the second electrode of the sixth transistor M6 (i.e., connected to the light-emitting element D)); and
the light emitting control sub-circuit (transistors M5 and M6 in Fig. 2) is electrically connected to
a first light emitting signal terminal (En1 light emitting signal terminal in Fig. 2), a second light emitting
signal terminal (En2 light emitting signal terminal in Fig. 2), a first power supply terminal (VDD power
supply terminal in Fig. 2), the second node (node directly connecting transistor M1 and M6 in Fig. 2), the
third node (node N2 in Fig. 2), and the fourth node respectively (node directly connecting transistor M6
and light emitting element D in Fig. 2), and is configured to provide a signal of the first power
supply terminal to the third node and a signal of the second node to the fourth node under control of
signals of the first light emitting signal terminal and the second light emitting signal terminal ([0104-
0106]: light emitting stage t4, signals En1 and En2 are active, transistor M5 and M6 are turned on.
First terminal of the first transistor M1 connected to the power supply terminal VDD, and the second
terminal of the first transistor M1 connected to the light-emitting element D, so that the transistor
M1 drives the light-emitting element D to emit light, Fig. 2), but does not explicitly disclose initial signal
terminal is second initial signal terminal.
However, Gao et al. teaches initial signal terminal is second initial signal terminal (Init2 signal
terminal in Fig. 5).
It would have obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the device of Cheng such that the initial signal terminal is second initial
signal terminal as taught by Gao et al. in order to reset light emission voltage of previous frame.
As to claim 15, Cheng teaches the pixel driving circuit as discussed above, wherein the driving sub-circuit comprises a third transistor (transistor M1 in Fig. 2), the light emitting control sub-circuit comprises a fifth transistor (transistor M5 in Fig. 2) and a sixth transistor (transistor M6 in Fig. 2), and the anode reset sub-circuit comprises a seventh transistor (transistor M8 in Fig. 2);
a control electrode of the third transistor (transistor M1 in Fig. 2) is electrically connected to the first node (node N1 in Fig. 2), a first electrode of the third transistor (transistor M1 in Fig. 2) is electrically connected to the third node (node N2 in Fig. 2), and a second electrode of the third transistor (transistor M1 in Fig. 2) is electrically connected to the second node (node directly connecting transistor M1 and M6 in Fig. 2) ;
a control electrode of the fifth transistor (transistor M5 in Fig. 2) is electrically connected to the
first light emitting signal terminal (En1 light emitting signal terminal in Fig. 2), a first electrode of the
fifth transistor (transistor M5 in Fig. 2) is electrically connected to the first power supply terminal (VDD
power supply terminal in Fig. 2), and a second electrode of the fifth transistor (transistor M5 in Fig. 2) is
electrically connected to the third node (node N2 in Fig. 2);
a control electrode of the sixth transistor (transistor M6 in Fig. 2) is electrically connected to the
second light emitting signal terminal (En2 light emitting signal terminal in Fig. 2), a first electrode of the
sixth transistor (transistor M6 in Fig. 2) is electrically connected to the second node (node directly
connecting transistor M1 and M6 in Fig. 2), and a second electrode of the sixth transistor (transistor M6
in Fig. 2) is electrically connected to the fourth node (node directly connecting transistor M6 and
light emitting element D in Fig. 2); and a control electrode of the seventh transistor (transistor M8 in Fig.
2) is electrically connected to the third scan signal terminal (S2n signal terminal in Fig. 2), a first
electrode of the seventh transistor (transistor M8 in Fig. 2) is electrically connected to the initial signal
terminal (Vini signal terminal in Fig. 2), and a second electrode of the seventh transistor (transistor M8
in Fig. 2) is electrically connected to the fourth node (node directly connecting transistor M6 and light
emitting element D in Fig. 2), but does not explicitly disclose initial signal terminal is second initial signal
terminal.
However, Gao et al. teaches initial signal terminal is second initial signal terminal (Init2 signal
terminal in Fig. 5).
It would have obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the device of Cheng such that the initial signal terminal is second initial
signal terminal as taught by Gao et al. in order to reset light emission voltage of previous frame.
Allowable Subject Matter
Claims 18-20, 22 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
Prosecution Insights