DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 2-4 and 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02 January 2026.
Applicant’s election without traverse of Species II, corresponding to originally filed Claims 1 and 5-7, in the reply filed on 02 January 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 5-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Independent Claim 1 recites “a first gate electrode of the second thin-film transistor is connected to any one of a second scan line and a third scan line…” wherein “brightness of the light-emitting element is controlled based on signals transmitted through the first scan line, the second scan line, the third scan line, and the data line and the first power voltage.” It is unclear how the claimed “first gate electrode” is connected to one of the “second scan line” and the “third scan line,” but the brightness of the claimed light-emitting element is controlled by both the “second scan line” and the “third scan line.”
Originally filed Figures 1A and 1B provide for a first pixel circuit (100) and a second pixel circuit (110), respectively. In this regard, originally filed Figures 1A and 1B appear to suggest that a claimed “first gate electrode” of a claimed “second thin-film transistor” (see (T2) in Figures 1A and 1B) is connected to one of the “second scan line” (Scan(n-1)) or the “third scan line” (Scan2(n)), but not both in a single pixel circuit. As such, originally filed Figures 1A and 1B appear to suggest that a brightness of a light-emitting element of a pixel circuit is controlled based on signals transmitted through either of the “second scan line” or the “third scan line,” but not both. Therefore, as best understood by the examiner, the claimed “second scan line” and the claimed “third scan line” reference only a single scan line in the display pixel circuit, and the claimed “second scan line” and “third scan line” are interpreted herein as corresponding to a single scan line.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kasai (US 2016 / 0211315) in view of Dewey et al. (hereinafter “Dewey” US 2020 / 0098925).
As pertaining to Claim 1, Kasai discloses (see Fig. 19) a display pixel circuit (110), comprising a first thin-film transistor (122), a second thin-film transistor (125), and a light-emitting element (130),
wherein a first gate electrode of the first thin-film transistor (122) is connected to a first scan line (Gwr), a second gate electrode is connected to a ground terminal (V4), a drain electrode is connected to a data line (114), and a source electrode is connected to a second gate electrode of the second thin-film transistor (125);
a first gate electrode of the second thin-film transistor (125) is connected to any one of a second scan line (V3) and a third scan line (V3 as interprets as the same scan line as the second scan line as addressed in 112 rejection above), a drain electrode is connected to a first power voltage (V1), and a source electrode is connected to a positive electrode of the light-emitting element (130);
a negative electrode of the light-emitting element (130) is connected to a second power voltage (V2); and
brightness of the light-emitting element (130) is controlled based on signals transmitted through the first scan line (Gwr), the second scan line (V3), the third scan line (V3), and the data line (114) and the first power voltage (V1; see Page 7, Para. [0122]-[0123] and Page 4, Para. [0077]).
Kasai does not explicitly disclose that the first thin-film transistor (122) has ferroelectric properties based on a gate-insulating film associated with at least one of the first and second gate electrodes of the first thin-film transistor; and the second thin-film transistor (125) has ferroelectric properties based on a gate-insulating film associated with at least one of the first and second gate electrodes of the second thin-film transistor.
However, in the same field of endeavor, Dewey discloses (see Fig. 1) that it was well-known in the art before the effective filing date of the claimed invention to implement thin-film transistors in display pixel circuits of a display device, wherein the thin-film transistors have ferroelectric properties based on a gate-insulating film associated with at least one of first and second gate electrodes of the thin-film transistor (see Page 1, Para. [0002]; Page 3, Para. [0020]; Page 4, Para. [0026]; and Page 7, Para. [0041]) in order to take advantage of the benefits offered by the ferroelectric-based transistor including a ferroelectric layer in the gate stack, namely an increase in electrical current and a fast turn-on time along with reduced leakage current when the thin-film transistors operate in an off-state (see Page 2, Para. [0015]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kasai with the teachings of Dewey, such that the first thin-film transistor (122) of Kasai has ferroelectric properties based on a gate-insulating film associated with at least one of the first and second gate electrodes of the first thin-film transistor; and the second thin-film transistor (125) of Kasai has ferroelectric properties based on a gate-insulating film associated with at least one of the first and second gate electrodes of the second thin-film transistor, as suggested by Dewey, in order to take advantage of the benefits offered by the ferroelectric-based transistor including a ferroelectric layer in the gate stack, namely an increase in electrical current and a fast turn-on time along with reduced leakage current when the thin-film transistors operate in an off-state.
As pertaining to Claim 5, Kasai discloses (see Fig. 19) that a second gate electrode of the first thin-film transistor (122) is connected to the ground terminal (V4) to remove ferroelectric properties of a second gate-insulating film of the first thin-film transistor (122; i.e., as a function of applying low voltage to a ferroelectric thin-film transistor), and thus the first thin-film transistor (122) has no memory characteristics and operates as a volatile switching thin-film transistor (122); and
a second gate electrode of the second thin-film transistor (125) is connected to a source electrode of the first thin-film transistor (122) so that the second thin-film transistor (125) has non-volatile memory characteristics due to ferroelectric properties of a second gate-insulating film of the second thin-film transistor (125; i.e., as a function of applying a high voltage to a ferroelectric thin-film transistor), and thus the second thin-film transistor (125) operates as a non-volatile driving thin-film transistor (see Page 7, Para. [0122]-[0123] of Kasai in combination with Page 2, Para. [0015] of Dewey which describes the function of the ferroelectric thin-film transistor).
As pertaining to Claim 6, Kasai discloses (see Fig. 19) that, in the second thin-film transistor (125), one frame (i.e., a driving period for displaying an image) is divided into a plurality of sub-frames (i.e., arbitrary time periods within a frame) and a luminous state (i.e., an arbitrary on/off state) of the light-emitting element (130) in which brightness of the light-emitting element (130) is controlled is maintained (i.e., for an arbitrary time period) for the one frame (i.e., the driving period) based on the non-volatile memory characteristics (again, see Page 4 through Page 5, Para. [0082]-[0085], for example, and Page 7, Para. [0122]-[0123] of Kasai in combination with Page 2, Para. [0015] of Dewey).
As pertaining to Claim 7, Kasai discloses (see Fig. 19) that the number of operating sub-frames (i.e., arbitrary time periods within a frame) is determined depending on time when the first power voltage (V1) is applied as a high voltage in the sub-frames (i.e., the arbitrary time periods within a frame), and brightness of the light-emitting element (130) increases as the determined number of sub-frames (i.e., arbitrary time periods within a frame) increases (i.e., as an “on time” of the light-emitting element increases, based on the time when the driving voltage (V1) is applied as a high voltage, the overall brightness of the light-emitting element increases; again, see Page 4 through Page 5, Para. [0082]-[0085], for example, and Page 7, Para. [0122]-[0123]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US 2014 / 0354698) discloses (see Fig. 2) a means of controlling dimming in a pixel circuit by maintaining an on-time of a driving transistor and adjusting a driving voltage (ELVDD).
Then et al. (US 2019 / 0058049) suggests the implementation of ferroelectric-based transistors in display devices for enhanced on-state and off-state performance.
Yoon et al. (US 2012 / 0007158) discloses a double-gate ferroelectric thin film transistor for usage in a display device.
Huitema et al. (US 2008 / 0259066) discloses a method for addressing active matrix displays with ferroelectric thin film transistor pixels.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623