DETAILED ACTION
The instant action is in response to application 19 September 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to for the following informalities:
The title is objected to as not being descriptive. Examiner suggests Balancing DC Capacitors in a Neutral-Point Clamped Inverter
The background section is required to include the oldest filed copending application, which appears to be the WIPO document. It is also ordinary and customary to include copending applications filing dates and publication dates (if available).
The first sentence in ¶13 appears to be a run-on sentence and is not proper English grammar. Applicant is cordially advised that they are only limited to one sentence in the claims.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for domestic priority based on a PCT application filed in Japan on 25 March 2022.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Yamanaka (US 6490185).
As to claim 1, Yamanaka teaches A power conversion device comprising: an inverter including a plurality of switching elements (Fig. 1, items 24-35), the inverter receiving input of a DC voltage from a DC voltage source (Fig. 1, rectifier 2) and converting the DC voltage into a variable voltage variable frequency AC voltage (Col. 1, lines 10-15, “variable speed”) to output the AC voltage to a load (Fig. 1, item 36); a control unit circuit that controls on/off drive of the plurality of switching elements under PWM control (Fig. 5); and a series body of a positive electrode side capacitor (Fig. 1, 3) and a negative electrode side capacitor (Fig. 1, 4) connected between a positive electrode and a negative electrode of the DC voltage source on an input side of the inverter, wherein an output potential of the inverter at least has a potential of the positive electrode and a potential of the negative electrode of the DC voltage source and a potential of a neutral point which is a point of connection between the positive electrode side capacitor and the negative electrode side capacitor (Fig. 1, has the potentials P, 0, N which correspond to the positive, neutral, and negative voltages), and the control unit circuit includes a modulation factor computing unit circuit that computes a modulation factor of the inverter based on the DC voltage (Col. 1, lines 30-35 “when a potential difference between a neutral point voltage (voltage of a connection point O of serial-connected smoothing capacitors of the inverter) and a negative bus voltage is Vcn, in the neutral point potential control, Vcn must be controlled to be a half voltage of a bus voltage Vpn of the inverter.”) and an output voltage command value (a motor has a known voltage/frequency ratio, and this would be set by the controller to force a certain speed), a gate signal generator circuit that generates a gate signal necessary for on/off drive of the switching elements for generation of a pulse train based on comparison between the computed modulation factor and a carrier signa (Fig. 18, 104, 105), and a gate signal allocator circuit (Fig. 18, abstract “A method for controlling a neutral point potential of an inverter of neutral point clamping type irrespective of the power factor by measuring or predicting the phase current in a simple way. An output state taken by an inverter of three-phase neutral point clamping type is represented by a vector. Depending on the phase state where the voltage vector outputted from the inverter is contained between which vectors, the occurrence time ratio of a specific vector corresponding to the voltage vector is changed to stabilize the neutral point voltage.”) that adjusts allocation of the gate signal such that a voltage of the positive electrode side capacitor and a voltage of the negative electrode side capacitor are balanced.
Claim(s) 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tada (WO 2020261556A1).
Examiner note: US 20220302820 is being used as a translation of the WIPO document.
As to claim 1, Tada discloses A power conversion device comprising: an inverter including a plurality of switching elements (Fig. 2, items 6), the inverter receiving input of a DC voltage from a DC voltage source (Fig. 2, 1u) and converting the DC voltage into a variable voltage variable frequency AC voltage (claim 1 “variable frequency”) to output the AC voltage to a load (Fig. 2, item 3); a control unit circuit that controls on/off drive of the plurality of switching elements under PWM control (Fig. 25, 12u); and a series body of a positive electrode side capacitor (Fig. 2, 5a) and a negative electrode side capacitor (Fig. 2, 5b) connected between a positive electrode and a negative electrode of the DC voltage source on an input side of the inverter, wherein an output potential of the inverter at least has a potential of the positive electrode and a potential of the negative electrode of the DC voltage source and a potential of a neutral point which is a point of connection between the positive electrode side capacitor and the negative electrode side capacitor (Fig. 2, has the potentials 1u, 1u-5a, and 1u-5a-5b which correspond to the positive, neutral, and negative voltages), and the control unit circuit includes a modulation factor computing unit circuit that computes a modulation factor of the inverter based on the DC voltage and an output voltage command value (Claim 1, “calculating a modulation factor for the inverter on the basis of the DC voltage of the DC voltage source and the output voltage command value,” ), a gate signal generator circuit that generates a gate signal necessary for on/off drive of the switching elements for generation of a pulse train based on comparison between the computed modulation factor and a carrier signa (Fig. 25, 1240, 1250), and a gate signal allocator circuit (Fig. 25, item 128, Fig. 26 item S203) that adjusts allocation of the gate signal such that a voltage of the positive electrode side capacitor and a voltage of the negative electrode side capacitor are balanced.
As to claim 2, Tada discloses wherein the inverter includes a plurality of switching circuits, and the gate signal allocator (Fig. 25, item 16) circuit further includes a pulse distributor that sequentially allocates the gate signal necessary for on/off drive of switching elements in the plurality of switching circuits and allocates pulse generation to the plurality of switching circuits.
As to claim 3, Tada discloses wherein the pulse distributor allocates an order such that the plurality of switching circuits are alternately turned on, in connection with the gate signal necessary for on/off drive of the switching elements in the plurality of switching circuits (the gate signal driver follows the control logic).
As to claim 4, Tada discloses wherein the gate signal allocator circuit further includes a neutral point potential switching control unit that determines, when an absolute value of a difference between the voltage of the positive electrode side capacitor and the voltage of the negative electrode side capacitor exceeds a threshold value (Fig. 5, S203), whether the difference will further increase, based on allocation of the gate signal (Fig. 5, S204), and changes allocation of the gate signal to the switching elements in the plurality of switching circuits such that the difference will decrease when the gate signal allocator circuit determines that the difference will increase (Fig. 5, S205/206).
As to claim 5, Tada discloses wherein the gate signal allocator circuit further includes a neutral point potential switching control unit that determines, when an absolute value of a difference between the voltage of the positive electrode side capacitor and the voltage of the negative electrode side capacitor exceeds a threshold value (Fig. 5, S203), whether the difference will further increase, based on allocation of the gate signal (Fig. 5, S204), and changes allocation of the gate signal to the switching elements in the plurality of switching circuits such that the difference will decrease when the gate signal allocator circuit determines that the difference will increase (Fig. 5, S205/206).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 11923759. Although the claims at issue are not identical, they are not patentably distinct from each other because the patented document appears to have more limitations.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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