DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 21 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the applicant has provided evidence that the applicant intends the term "computer-readable medium” to include non-statutory matter. The applicant describes that a computer-readable medium may be transitory or non-transitory (see page 16, lines 31 - 37). The words "storage" and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claim(s) is/are drawn to a form of energy. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter.
The Examiner suggests amending the claim(s) to read as a “non-transitory computer-readable medium”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 5 – 6, 8 – 10, 12, and 18 – 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koufaty et al. US Patent Application Publication No. 2020/0019515 (originally cited in IDS filed 9/19/2024, hereinafter referred to as Koufaty).
Regarding claim 1, Koufaty describes an apparatus comprising: address translation circuitry configured to translate (These permissions… may be maintained on behalf of system software by the translation agent 130 in an HPT 135… (page 3, paragraph [0028]). According to one embodiment, the response of translation agent (e.g., the IOMMU) in the form of permission delivery or an error response, after the HPT walk has been completed, differs depending on whether the HPT walk was performed in response to translation request or a translated request… (page 4, paragraph [0039])), in response to an advance address translation request issued by a requester device on behalf of a given software context and specifying a given virtual address (Embodiments described herein are directed to providing secure address translation service by a translation agent based on a context of a requesting device (page 1, paragraph [0015]). At block 550, the translation agent performs translation request processing, including among other things, translating the specified VA to an HPA… (page 6, paragraph [0053])), the given virtual address into a given physical address and to provide the given physical address to the requester device to be associated with a subsequent translated access request issued by the requester device (At block 550, the translation agent performs translation request processing, including among other things, translating the specified VA to an HPA… (page 6, paragraph [0053]). At block 810, the translation agent translates the VA specified in the ATS translation request to an HPA and determines the page table permissions and page size associated with this virtual address… (page 7, paragraph [0077])); and translated access control circuitry (At block 560, the translation agent performs translated request processing… (page 6, paragraph [0054])) responsive to a translated access request issued by the requester device on behalf of the given software context and specifying a target physical address (At block 560, the translation agent performs translated request processing, including, among other things, verifying page access permission of the context of the device to perform the requested memory operation… (page 6, paragraph [0054])), to: look up, based on the target physical address, corresponding permissions information indicative of corresponding access permissions defined in a device permission table (Embodiments described herein generally seek to provide an access control mechanism, so that a device can only access HPAs that were explicitly assigned to a context of the device initiating a memory operation at issue. For example, a host permission table (HPT) can be configured (at a desired granularity) by trusted system software to allow access to certain HPAs and enforced by hardware (e.g., the IOMMU) (page 2, paragraph [0018])) for a region of physical address space encompassing the target physical address, wherein the corresponding access permissions provide information for checking whether translated access requests from a plurality of software contexts are prohibited (At block 610, the translation agent determines page access permissions associated with the HPA specified in the ATS translated request (page 6, paragraph [0060])); determine, based on the corresponding permissions information, whether the given software context is prohibited from accessing a target memory location corresponding to the target physical address in response to translated access requests (At decision block 620, based on the page access permissions determined at block 610, the translation agent makes a determination regarding whether the memory operations specified by the ATS translated request is permitted… (page 6, paragraph [0061])); and when it is determined that the given software context is prohibited from accessing the target memory location in response to translated access requests, trigger an error response (At block 640, the translation agent blocks the memory operation. In one embodiment, write operations may be dropped to avoid memory corruptions and read operations can return an Unsupported Request (UR) to the device. Additionally, or alternatively, the translation agent may log any errors and notify the host via existing fault logging mechanisms (page 6, paragraph [0063])).
Regarding claim 2, Koufaty describes the apparatus of claim 1 (see above), wherein the translated access control circuitry is configured to support at least one encoding of an entry of the device permissions table that identifies at least one access permission associated with an identified software context specified from among a plurality of software contexts by the entry of the device permissions table (For example, a translation agent of a host system may maintain on behalf of system software and make use of or otherwise consult an HPT during translation request processing and/or translated request processing that associates a page permissions entry containing page access permissions with each physical page of multiple physical pages in a memory of the host system and each of multiple contexts of multiple devices coupled to the host system… (page 2, paragraph [0020])).
Regarding claim 3, Koufaty describes the apparatus of claim 1 (see above), wherein the translated access control circuitry is configured to support the device permission table comprising a plurality of entries indexed by physical address (Fig. 2 is a block diagram illustrating how various portions of a host physical address (HPA) 210 are used to walk through a multi-level HPT 260… (page 3, paragraph [0032])), wherein each of the plurality of entries is shared between the plurality of contexts and identifies an access permission for an associated region of physical address space (…if the request at issue relates to a page that is outside the scope of the HPT 260, the access is denied… (page 4, paragraph [0036]). …finally, the L1 entry 251 of the L1 table 250 will contain the page access permissions of the HPA 210 (page 4, paragraph [0038]). …In this manner, any attempt to access a physical address within a memory page that has not been configured by system software will be disallowed by the translation agent, thereby allowing the system software to focus on selectively configuring page access permissions for memory pages expressly being authorized for access by particular contexts of devices (page 4, paragraph [0042])).
Regarding claim 5, Koufaty describes the apparatus of claim 1 (see above), wherein: the translated access control circuitry is configured to look up, based on a device identifier specified in the translated access request, corresponding device configuration information indicative of the given software context associated with the device identifier; and when the corresponding permissions information specifies said at least one access permission associated with the identified software context, the translated access control circuitry is configured to determine whether the given software context is prohibited from accessing the target memory location in response to translated access requests based on a comparison of the given software context and the identified software context (…a translation agent of a host system may maintain on behalf of system software and make use of or otherwise consult an HPT during translation request processing and/or translated request processing that associates a page permission entry containing page access permissions with each physical page of multiple physical pages in a memory of the host system and each of multiple contexts of multiple devices couped to the host system (page 2, paragraph [0020]). …the permission entry includes at least page access permissions indicating whether the context of the device is permitted to read the page to which the permission entry corresponds and indicating whether the context of the device is permitted to write the page (page 2, paragraph [0024]). For instance, using the request’s Bus/Device/Function (BDF) descriptor, the IOMMU can obtain the associated Context Entry. If HPT has been enabled for the device in that Context Entry, the HPT is checked to obtain the associated page access permissions… (page 6, paragraph [0057])).
Regarding claim 6, Koufaty describes the apparatus of claim 5 (see above) wherein the translated access control circuitry is configured to support the device configuration table comprising a plurality of entries indexed by device identifier, wherein each of the plurality of entries identifies device configuration information for an associated device (In one embodiment, system software (e.g., the operating system (not shown), virtual machine manager (VMM) 115 and/or virtual machines 116a-n) running on the host system can configure permissions (e.g., read and/or write access) for each page of memory 140 individually for each of devices 141a-c… (page 3, paragraph [0028]). …the HPT 135 could be represented as a flat table in memory 140 in which for every device associated with the host system that is desired to use secure ATS and for each page in main memory a corresponding permission entry containing page access permissions specifying appropriate read/write permissions can be created (page 3, paragraph [0029])).
Regarding claim 8, Koufaty describes the apparatus of claim 1 (see above), comprising a device permission cache configured to store permissions information corresponding to a subset of access permissions defined in the device permission table, wherein the translated access control circuitry is responsive to the translated access request to look up, based on the target physical address of the translated access request, the corresponding permissions information in the device permission cache (…in order to avoid pre-allocating a large memory space take advantage of the small size of the permission entries, the HPT 135 can be organized as a hierarchical table (similar to how address translation page tables are organized)… In any implementations in which the HPT 135 is stored off-chip, one or more optional, dedicated HPT caches 131 may be used to accelerate walking of the various levels of the HPT 135 (page 3, paragraph [0029])).
Regarding claim 9, Koufaty describes the apparatus of claim 8 (see above), wherein the translated access control circuitry is responsive to the advance address translation request to determine the corresponding permissions information for the region of physical address space encompassing the target physical address, and to store the corresponding permissions information to the device permission cache (…dedicated HPT caches 131 may be used to accelerate walking of the various levels of the HPT 135 (page 3, paragraph [0029])).
Regarding claim 10, Koufaty describes the apparatus of claim 8 (see above), wherein: the address translation circuitry is configured to look up, in response to the advance address translation request, a set of translation table permissions defined in an address translation table entry corresponding to the given virtual address and the given software context; and the translated access control circuitry is configured to determine the corresponding permissions information in dependence on the translation table permissions, and to store the corresponding permissions information to the device permission cache (page 3, paragraph [0029]).
Regarding claim 12, Koufaty describes the apparatus of claim 1 (see above), comprising device permission table walk circuitry configured to look up a multi-level table representing the device permission table, wherein: each level of the multi-level table comprises entries associated with successively smaller regions of the physical address space; a final level of the multi-level page table defines the access permissions; and each level other than the final level defines pointers to a plurality of tables in the next level, the pointers being selectable based on a portion of a physical address (…walk through a multi-level HPT 260… (page 3, paragraph [0032]). ...When the top-level HPT result indicates the top-level entry contains a valid next-level HPT table address (a valid pointer), then processing continues to block 730 to continue the HPT walk (page 6, paragraph [0066])).
Regarding claim 18, Koufaty describes the apparatus of claim 1 (see above) wherein the translated access control circuitry is configured to support, as the device permission table, a table shared between a plurality of devices to define access permissions for translated accesses issued by the plurality of devices (In one embodiment, system software (e.g., the operating system (not shown), virtual machine manager (VMM) 115 and/or virtual machines 116a-n) running on the host system can configure permissions (e.g., read and/or write access) for each page of memory 140 individually for each of devices 141a-c. These permissions… may be maintained on behalf of system software by the translation agent 130 in an HPT 135… (page 3, paragraph [0028])).
Regarding claim 19, Koufaty describes the apparatus of claim 1 (see above) comprising: a device permission cache configured to store permissions information corresponding to a subset of access permissions defined in the device permission table; processing circuitry configured to execute software; and device permission cache control circuitry configured to invalidate entries in the device permissions cache in response to a device permission cache maintenance command triggered by the software executing on the processing circuitry and having a different encoding to a translation look-aside buffer invalidation command for triggering invalidation of page table information from a translation look-aside buffer (At block 510, the translation agent receives a request (e.g., a request from a processor (e.g., CPUs 110) or an ATS translated request or ATS translation request from a device (e.g., devices 141a-c)). As described further below a request from a processor would typically represent a request to configure the HPT or a request to invalidate entries within the optional HPT cache(s) (e.g., HPT cache(s) 131) (page 5, paragraph [0049]). At block 530, a request has been received from the CPU to configure the HPT or to invalidate one or more cache entries. Responsive to the request, the translation agent updates the HPT or updates the optional HPT cache(s) as appropriate. In some embodiments, the update of the HPT is performed exclusively by software (page 5, paragraph [0051])).
Regarding claim 20, Koufaty describes a method comprising: in response to an advance address translation request issued by a requester device on behalf of a given software context and specifying a given virtual address (Embodiments described herein are directed to providing secure address translation service by a translation agent based on a context of a requesting device (page 1, paragraph [0015]). At block 550, the translation agent performs translation request processing, including among other things, translating the specified VA to an HPA… (page 6, paragraph [0053])), translating the given virtual address into a given physical address and providing the given physical address to the requester device to be associated with a subsequent translated access request issued by the requester device (At block 550, the translation agent performs translation request processing, including among other things, translating the specified VA to an HPA… (page 6, paragraph [0053]). At block 810, the translation agent translates the VA specified in the ATS translation request to an HPA and determines the page table permissions and page size associated with this virtual address… (page 7, paragraph [0077])); and in response to a translated access request, issued by the requester device on behalf of the given software context and specifying a target physical address (At block 560, the translation agent performs translated request processing, including, among other things, verifying page access permission of the context of the device to perform the requested memory operation… (page 6, paragraph [0054])), translated access control circuitry performing steps of: looking up, based on the target physical address, corresponding permissions information indicative of corresponding access permissions defined in a device permissions table (Embodiments described herein generally seek to provide an access control mechanism, so that a device can only access HPAs that were explicitly assigned to a context of the device initiating a memory operation at issue. For example, a host permission table (HPT) can be configured (at a desired granularity) by trusted system software to allow access to certain HPAs and enforced by hardware (e.g., the IOMMU) (page 2, paragraph [0018])) for a region of physical address space encompassing the target physical address, wherein the corresponding access permissions provide information for checking whether translated access requests from a plurality of software contexts are prohibited (At block 610, the translation agent determines page access permissions associated with the HPA specified in the ATS translated request (page 6, paragraph [0060])); determining, based on the corresponding permissions information, whether the given software context is prohibited from accessing a target memory location corresponding to the target physical address in response to translated access requests (At decision block 620, based on the page access permissions determined at block 610, the translation agent makes a determination regarding whether the memory operations specified by the ATS translated request is permitted… (page 6, paragraph [0061])); and when it is determined that the given software context is prohibited from accessing the target memory location in response to translated access requests, triggering an error response (At block 640, the translation agent blocks the memory operation. In one embodiment, write operations may be dropped to avoid memory corruptions and read operations can return an Unsupported Request (UR) to the device. Additionally, or alternatively, the translation agent may log any errors and notify the host via existing fault logging mechanisms (page 6, paragraph [0063])).
Regarding claim 21, Koufaty describes a computer-readable medium to store computer-readable code for fabrication of an apparatus comprising (Examples may include subject matter such as a method, means for performing acts of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method, or of an apparatus or system for facilitating hybrid communication according to embodiments and examples described herein (page 10, paragraph [0110])): address translation circuitry configured to translate (These permissions… may be maintained on behalf of system software by the translation agent 130 in an HPT 135… (page 3, paragraph [0028]). According to one embodiment, the response of translation agent (e.g., the IOMMU) in the form of permission delivery or an error response, after the HPT walk has been completed, differs depending on whether the HPT walk was performed in response to translation request or a translated request… (page 4, paragraph [0039])), in response to an advance address translation request issued by a requester device on behalf of a given software context and specifying a given virtual address (Embodiments described herein are directed to providing secure address translation service by a translation agent based on a context of a requesting device (page 1, paragraph [0015]). At block 550, the translation agent performs translation request processing, including among other things, translating the specified VA to an HPA… (page 6, paragraph [0053])), the given virtual address into a given physical address and to provide the given physical address to the requester device to be associated with a subsequent translated access request issued by the requester device (At block 550, the translation agent performs translation request processing, including among other things, translating the specified VA to an HPA… (page 6, paragraph [0053]). At block 810, the translation agent translates the VA specified in the ATS translation request to an HPA and determines the page table permissions and page size associated with this virtual address… (page 7, paragraph [0077])); and translated access control circuitry (At block 560, the translation agent performs translated request processing… (page 6, paragraph [0054])) responsive to a translated access request issued by the requester device on behalf of the given software context and specifying a target physical address (At block 560, the translation agent performs translated request processing, including, among other things, verifying page access permission of the context of the device to perform the requested memory operation… (page 6, paragraph [0054])), to: look up, based on the target physical address, corresponding permissions information indicative of corresponding access permissions defined in a device permission table (Embodiments described herein generally seek to provide an access control mechanism, so that a device can only access HPAs that were explicitly assigned to a context of the device initiating a memory operation at issue. For example, a host permission table (HPT) can be configured (at a desired granularity) by trusted system software to allow access to certain HPAs and enforced by hardware (e.g., the IOMMU) (page 2, paragraph [0018])) for a region of physical address space encompassing the target physical address, wherein the corresponding access permissions provide information for checking whether translated access requests from a plurality of software contexts are prohibited (At block 610, the translation agent determines page access permissions associated with the HPA specified in the ATS translated request (page 6, paragraph [0060])); determine, based on the corresponding permissions information, whether the given software context is prohibited from accessing a target memory location corresponding to the target physical address in response to translated access requests (At decision block 620, based on the page access permissions determined at block 610, the translation agent makes a determination regarding whether the memory operations specified by the ATS translated request is permitted… (page 6, paragraph [0061])); and when it is determined that the given software context is prohibited from accessing the target memory location in response to translated access requests, trigger an error response (At block 640, the translation agent blocks the memory operation. In one embodiment, write operations may be dropped to avoid memory corruptions and read operations can return an Unsupported Request (UR) to the device. Additionally, or alternatively, the translation agent may log any errors and notify the host via existing fault logging mechanisms (page 6, paragraph [0063])).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Koufaty in view of Trikalinou et al. US Patent Application Publication No. 2021/0026543 (originally cited in IDS filed 9/19/2024, herein after referred to as Trikalinou).
Regarding claim 4, Koufaty describes the apparatus of claim 3 (see above). wherein: the access permission comprises a device permission level selected from a plurality of device permission levels (…the permission entry includes at least page access permissions indicating whether the context of the device is permitted to read the page to which the permission entry corresponds and indicating whether the context device is permitted to write the page (page 2, paragraph [0024]). One could reasonably consider read permitted, read prohibited, write permitted, write prohibited, etc., as various permission levels). Koufaty does not specifically disclose the at least one permission level comprises at least one of: a private permission level identifying an identified software context of the plurality of software contexts and indicating that translated access requests associated with processes other than the identified software context are prohibited from accessing the associated region of physical address space; and a shared permission level identifying an identified software context of the plurality of software contexts and indicating that translated access requests associated with processes other than the identified software context and a supervisor process operating at a higher privilege level than plurality of software contexts are prohibited from accessing the associated region of physical address space.
Trikalinou describes secure address translation services for trust domain extensions. Specifically, according to one embodiment, [Trusted Domain – TD] translation components include both secure HPT 336, as well as shared EPT 340 and shared HPT 350. In such an embodiment, physical pages that are private to the TD and encrypted with the TD's private key(s) are marked in the secure HPT 336, while physical pages that are shared between TD and other VMs, TDs, or the hypervisor are marked in shared HPT 350 (page 3, paragraph [0040]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Trikalinou teachings in the Koufaty system. Skilled artisan would have been motivated to incorporate the method of indicating private page permissions and shared page permissions as taught by Trikalinou in the Koufaty system for effectively indicating page permissions to requesting devices. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as address translation services. This close relation between both of the references highly suggests an expectation of success.
Claims 7, 11, and 15 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Koufaty in view of Grocutt US Patent Application Publication No. 2021/0311884 (herein after referred to as Grocutt).
Regarding claim 7, Koufaty describes the apparatus of claim 6 (see above). Koufaty does not specifically disclose wherein: the device configuration information in each of the plurality of entries comprises privilege information indicating whether the associated device is prohibited from issuing translated access requests; the privilege information comprises a privilege level selected from a plurality of privilege levels; and the plurality of privilege levels include at least one privilege level indicating that the associated device is permitted to issue translated access requests even when the device permission table indicates that access to a subset of physical address space in response to translated access requests is prohibited for the at least one software context associated with the device identifier.
Grocutt describes a memory protection unit using memory protection table stored in a memory system. Specifically, the access permissions could specify whether a certain address region is read-only, or can be both readable and writable, or could specify which privilege levels are allowed to access the corresponding address region. It may also be desirable to control whether an area of memory is executable. Such execute permissions may be conditional on privilege level, for example it may be desirable to permit unprivileged execution on an area of memory but prohibit execution in a privileged mode (page 1, paragraph [0002]). The access permissions could also restrict access to the corresponding address region to certain exception levels or privilege levels of the processing circuitry 4, and the permission checking circuitry 40 could check whether a current exception level or privilege level associated with the memory access request meets the restrictions defined in the access permissions (page 15, paragraph [0106]). Enabling overlaps between static and memory-based MPU entries in this way can be useful for setting up permissions for a more privileged process which is able to access a wider range of the address space, and also to allow a less privileged process access only to a restricted subset of the address range available to the more privileged process (page 18, paragraph [0123]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Grocutt teachings in the Koufaty system. Skilled artisan would have been motivated to incorporate the method of using privilege level based permissions as taught by Grocutt in the Koufaty system for effectively avoiding the need to split a region into separate entries. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as access permissions. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 11, Koufaty describes the apparatus of claim 10 (see above). Koufaty does not specifically disclose wherein the translated access control circuitry is responsive to determining, based on the translation table permissions, that at least one of the corresponding access permissions for the given physical address is unknown from the translation table permissions, to set, as the corresponding permissions information to be stored to the device permission cache, a default access permission.
Grocutt describes a memory protection unit using memory protection table stored in a memory system. Specifically, in one example the permission checking circuitry may determine whether the at least one MPU memory access request is permitted based on a default set of access permissions specified independently of the memory protection table. Hence, by using a default set of permissions, which for example could be hardwired or specified in a configurable register of the MPU, there is no need to lookup the memory protection table in memory to determine whether the MPU is allowed to issue a memory access request to a particular address (page 8, paragraph [0066]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Grocutt teachings in the Koufaty system. Skilled artisan would have been motivated to incorporate the method of using a default set of permissions as taught by Grocutt in the Koufaty system for effectively avoiding the need to lookup the memory protection table, which can help improve real time handling. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as access permissions. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 15, Koufaty describes the apparatus of claim 1 (see above). Koufaty does not specifically disclose comprising a device permission cache configured to store permissions information corresponding to a subset of access permissions defined in the device permission table, wherein the translated access control circuitry is configured to support at least one encoding of an entry of the device permissions table indicating that access permissions for each of a plurality of regions of physical address space are identical and can be represented by a single entry in the device permission cache corresponding to a predetermined one of the plurality of regions.
Grocutt describes a memory protection unit using memory protection table stored in a memory system. Specifically, by permitting each region to have an arbitrary size corresponding to a number of bytes other than a power of 2, this means that each region can cover a large amount of memory and it is not necessary to subdivide regions intended to have the same access permissions into multiple separate entries (page 3, paragraph [0040]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Grocutt teachings in the Koufaty system. Skilled artisan would have been motivated to incorporate the method of using arbitrary sized regions as taught by Grocutt in the Koufaty system for effectively avoiding the need to subdivide regions intended to have the same access permissions into multiple separate entries. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as access permissions. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 16, Koufaty describes the apparatus of claim 1 (see above). Koufaty does not specifically disclose wherein: the translated access request is associated with a security state selected from amongst a plurality of possible security states; and the lookup of the corresponding permissions information is based on the security state and the target physical address.
Grocutt describes a memory protection unit using memory protection table stored in a memory system. Specifically, the processing circuitry may allow operation in a plurality of security states, each state may be sub divided into a plurality of privilege levels. The processing circuitry may permit fast transitions between security states. Each of the plurality of security states may have an associated memory protection table to be used when the processing circuitry is executing instructions in that security state (page 6, paragraph [0056]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Grocutt teachings in the Koufaty system. Skilled artisan would have been motivated to incorporate the method of including a plurality of security states as taught by Grocutt in the Koufaty system for effectively providing additional permission configuration. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as access permissions. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 17, Koufaty in view of Grocutt describe the apparatus of claim 15 (see above), wherein the translated access control circuitry is configured to support a plurality of device permission tables, each corresponding to a different security state (Grocutt, page 6, paragraph [0056]).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Koufaty in view of Abhishek Raja US Patent Application Publication No. 2019/0188149 (herein after referred to as Abhishek Raja).
Regarding claim 13, Koufaty describes the apparatus of claim 12 (see above). Koufaty does not specifically disclose wherein at least one of: an upper limit of a number of levels of the multi-level table supported by the device permission table walk circuitry is less than an upper limit of the number of levels of page tables supported by page table walk circuitry an the device permission table walk circuitry is configured to support at least one encoding of an entry of at least one level other than the final level indicating an access permission that applies to an entire block of physical address space covered by that entry at said at least one level other than the final level.
Abhishek Raja describes an address translation cache. Specifically, for example, the final level descriptors may be page descriptors or block descriptors as discussed in the Arm Architecture Reference Manual, page descriptors being obtained at a final provided level of the page table walk process, whilst block descriptors can be reached before the final level of a page table walk process. In some instances, such page descriptors are also referred to as leaf descriptors (page 5, paragraph [0047]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Abhishek Raja teachings in the Koufaty system. Skilled artisan would have been motivated to incorporate the method of a page walk table including block descriptors before the final level of the table as taught by Abhishek Raja in the Koufaty system for effectively providing broader levels of identification of memory areas before a final level identifying a more granular level of identification. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as access permissions. This close relation between both of the references highly suggests an expectation of success.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth M Lo can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RALPH A VERDERAMO III/Examiner, Art Unit 2136
rv
January 8, 2026
/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2136