DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/20/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 3, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaput (US 20180130940 - IDS) in view of Thieringer et al. (US 20120228938).
Claims 1 and 10; Chaput discloses a drive circuit comprising: a buck-boost circuit (120) configured to operate in a corresponding voltage regulation mode according to a control signal (gating signal of Q1 and/or Q2) for voltage regulation, so as to convert an input voltage (Vin) into an unipolar folded signal (e.g. output of Q2) and output the folded signal; a full-bridge inverter circuit (160) connected to the buck-boost circuit (120) and configured to invert polarities of part of the folded signal according to a polarity inversion signal (control signal for Q3-Q6), in order to expand the folded signal into a target drive signal (Vout) and output the target drive signal (e.g. to load 165); and a control circuit connected to the buck-boost circuit (120) and the full-bridge inverter circuit (160) and configured to generate the control signal for voltage regulation and the polarity inversion signal according to a reference signal (Vref), wherein the reference signal corresponds to the target drive signal (Vout).
However, Chatput does not disclose whether the voltage regulation mode comprises a reverse boost mode or a forward buck mode.
Thieringer et al. teach a DC-AC inverter assembly. The inverter includes a semiconductor bridge circuit and wherein a DC chopper controller is provided for creating half-waves of an AC voltage on the output side and the bridge circuit is connected downstream of the DC chopper controller and acts as pole changer on the half-waves. Fig. 4 shows a buck boost regulator with forward boost mode, reverse boost mode, forward buck mode, and reverse buck mode.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Chatput to include a buck boost regulator with forward boost mode, reverse boost mode, forward buck mode, and reverse buck mode in order to provide a DC-AC inverter assembly, as taught by Thieringer et al., that includes a semiconductor bridge circuit and wherein a DC chopper controller is provided for creating half-waves of an AC voltage on the output side and the bridge circuit is connected downstream of the DC chopper controller and acts as pole changer on the half-waves.
Claims 2 and 11; Thieringer et al. also teach the buck-boost circuit can comprises a first switching transistor (S1_Tss), a second switching transistor (S2_Tss), a third switching transistor (S1_Hss), a fourth switching transistor (S2_Hss) and a first inductor (L); wherein a first conductive terminal of the first switching transistor (S1) is connected to an input positive electrode (U1) of the buck-boost circuit, a second conductive terminal of the first switching transistor (S1) is connected to a first conductive terminal of the second switching transistor (S2), and a second conductive terminal of the second switching transistor is connected to an input negative electrode (U1) of the buck-boost circuit; wherein both the input positive electrode and the input negative electrode are configured to receive the input voltage (U1); a first conductive terminal of the third switching transistor (S1_Hss) is connected to an output positive electrode of the buck-boost circuit, a second conductive terminal of the third switching transistor (S1_Hss) is connected to a first conductive terminal of the fourth switching transistor (S2_Hss), and a second conductive terminal of the fourth switching transistor is connected to an output negative electrode (gnd) of the buck-boost circuit; control terminals of the first switching transistor, the second switching transistor, the third switching transistor and the fourth switching transistor are connected in common to the control circuit, in order to receive the control signal for voltage regulation; the first inductor (L) is connected between the second conductive terminal of the first switching transistor and the second conductive terminal of the third switching transistor; and the input negative electrode is connected to the output negative electrode.
Claims 3 and 12; Chatput capacitor C1; (Thieringer et al. capacitor C_Tss).
Claims 6 and 17; Chatput shows a full bridge inverter 160 configured as claimed.
Claim(s) 4, 5 and 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaput and Thieringer et al. in view of Coles (US 20090102440).
Claims 4, 13 and 14; Chaput and Thieringer et al. disclose the claimed subject matter in regards to claims 1 and 10 supra, except for expressly disclosing when the buck-boost circuit is operated in the forward boost mode and the reverse buck mode according to the control signal for voltage regulation, the first switching transistor remains in a switched-on state, the second switching transistor remains in a switched-off state, the third switching transistor and the fourth switching transistor are complementarily switched-on.
Coles teaches, figure 4B, that when a buck boost is operating in forward mode switch VA is ON, VB is OFF, and VC & VD are toggled in order to provide boost operation.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Chatput and Thieringer et al. to include the ordinary boost mode operation by having the first switching transistor remain in a switched-on state, the second switching transistor remain in a switched-off state, the third switching transistor and the fourth switching transistor are complementarily switched-on in order to boost the input voltage and provide the boosted voltage to the load as taught by Coles.
Claims 5, 15 and 16; Chaput and Thieringer et al. disclose the claimed subject matter in regards to claims 1 and 10 supra, except for expressly disclosing when the buck-boost circuit operates in the forward buck mode and the reverse boost mode according to the control signal for voltage regulation, the first switching transistor and the second switching transistor are complementarily switched-on, the third switching transistor remains in a switched-on state, and the fourth switching transistor remains in a switched-off state.
Coles teaches, figure 4B, that when a buck boost is operating in forward mode switch VA & VB are toggled, and VC is OFF and VD is ON in order to provide buck operation.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Chatput and Thieringer et al. to include the ordinary buck mode operation by having the first switching transistor and the second switching transistor complementarily switched-on, the third switching transistor remains in a switched-on state, and the fourth switching transistor remains in a switched-off state in order to buck the input voltage and provide the bucked voltage to the load as taught by Coles.
Claim(s) 8, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaput and Thieringer et al. in view of Cuk (US 6388896).
Claims 8 and 19; Chaput and Thieringer et al. disclose the claimed subject matter in regards to claim 1 supra, except for a second inductor, a third inductor, a ninth switching transistor, a tenth switching transistor, a second capacitor, and a third capacitor; the second inductor, the second capacitor and the third inductor are sequentially connected in series between an input positive electrode of the buck-boost circuit and an output positive electrode of the buck-boost circuit; a first conductive terminal of the ninth switching transistor is connected to a first end of the second inductor, and a second conductive terminal of the ninth switching transistor is connected to an input negative electrode of the buck-boost circuit; a first conductive terminal of the tenth switching transistor is connected to a second end of the second inductor, and a second conductive terminal of the tenth switching transistor is connected to an output negative electrode of the buck-boost circuit; and the third capacitor is connected between the output positive electrode and the output negative electrode, and the output negative electrode is connected to the input negative electrode.
Cuk, figure 39a, teaches a second inductor (L1), a third inductor (L2), a ninth switching transistor (S1), a tenth switching transistor (S1’), a second capacitor (C1), and a third capacitor (C2); wherein the second inductor (L1), the second capacitor (C1) and the third inductor (L2) are sequentially connected in series between an input positive electrode (Vg) of the buck-boost circuit and an output positive electrode (V2/C2/R) of the buck-boost circuit; a first conductive terminal of the ninth switching transistor (S1) is connected to a first end of the second inductor (L1), and a second conductive terminal of the ninth switching transistor (S1) is connected to an input negative electrode of the buck-boost circuit (low side of Vg); a first conductive terminal of the tenth switching transistor (S1’) is connected to a second end of the second inductor (L1), and a second conductive terminal of the tenth switching transistor (S1’) is connected to an output negative electrode (low end of Lm) of the buck-boost circuit; and the third capacitor (C2) is connected between the output positive electrode and the output negative electrode, and the output negative electrode is connected to the input negative electrode.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Chatput and Thieringer et al. to configure the buck boost converter as claimed in order to provide a switching converter that operates at high efficiency, is small in size and light weight and enables ultra-high overload current capability as well as eliminates switching losses and reduces the magnetics size.
Claims 9 and 20; Chaput and Thieringer et al. disclose the claimed subject matter in regards to claim 1 supra, except for the buck-boost circuit comprises a fourth inductor, a fifth inductor, an eleventh switching transistor, a twelfth switching transistor, a fourth capacitor, and a fifth capacitor; wherein the fourth inductor is connected between a first conductive terminal of the eleventh switching transistor and an input positive electrode of the buck-boost circuit, and a second conductive terminal of the eleventh switching transistor is connected to an input negative electrode of the buck-boost circuit; a first conductive terminal of the twelfth switching transistor is connected to an output positive electrode of the buck-boost circuit, a second conductive terminal of the twelfth switching transistor is connected to the first conductive terminal of the eleventh switching transistor, and the fifth inductor is connected between the second conductive terminal of the twelfth switching transistor and an output negative electrode of the buck-boost circuit; and the fourth capacitor is connected between the input negative electrode and the output negative electrode, and the fifth capacitor is connected between the output positive electrode and the output negative electrode.
Cuk, figure 32f, teaches a fourth inductor (L1), a fifth inductor (Lm), an eleventh switching transistor (S1), a twelfth switching transistor (S’2), a fourth capacitor (C1), and a fifth capacitor (C2); wherein the fourth inductor (L1) is connected between a first conductive terminal of the eleventh switching transistor (S1) and an input positive electrode (of Vg) of the buck-boost circuit, and a second conductive terminal of the eleventh switching transistor (S1) is connected to an input negative electrode (-Vg) of the buck-boost circuit; a first conductive terminal of the twelfth switching transistor (S’2) is connected to an output positive electrode (L2/V2) of the buck-boost circuit, a second conductive terminal of the twelfth switching transistor (S’2) is connected to the first conductive terminal of the eleventh switching transistor (S1), and the fifth inductor (Lm) is connected between the second conductive terminal of the twelfth switching transistor (S’2) and an output negative electrode of the buck-boost circuit; and the fourth capacitor (C1) is connected between the input negative electrode and the output negative electrode, and the fifth capacitor (C2) is connected between the output positive electrode and the output negative electrode.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Chatput and Thieringer et al. to configure the buck boost converter as claimed in order to provide a switching converter that operates at high efficiency, is small in size and light weight and enables ultra-high overload current capability as well as eliminates switching losses and reduces the magnetics size.
Allowable Subject Matter
Claims 7 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20110012551 Tseng et al. disclose a boost/buck circuit; US 20090168460 Huang et al. disclose a DC/AC inverter with DC-DC converter; US 11081635 Delano et al. disclose an apparatus for driving a piezoelectric transducer.
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/GARY L LAXTON/ Primary Examiner, Art Unit 2838 6/12/2026
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