DETAILED ACTION
Claims 1-15 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9, 10, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schrey et al (US 2009/0251579 A1).
As per claim 1, Schrey discloses an image sensor assembly (figs. 1 and 4, image sensor circuit), comprising:
a pixel circuit comprising a first amplification transistor (fig. 4, image sensor circuit, source follower Q2) and a first selection transistor (fig. 4, image sensor circuit, selector switch Q3), wherein the first amplification transistor and the first selection transistor are electrically connected in series and are configured to output first pixel signals at a first pixel output, when the first selection transistor is turned on (fig. 4, image sensor circuit, source follower Q2 and selector switch Q3 are connected in series, outputs first pixel signal, see para 0038); and
a converter circuit (fig. 4, image sensor circuit, converter circuit will be elements after selector switch Q3) configured to receive the first pixel signals from the first selection transistor and to receive second pixel signals from the first selection transistor or from a second selection transistor (fig. 4, image sensor circuit, differential amplifier, is configured to receive a first and second pixel signal (S1 and S2) from selector switch Q3), and to convert voltage differences between the first pixel signals and the second pixel signals into digital coefficients (fig. 4, image sensor circuit, differential amplifier converts the differences from the first and second signals and analog-to-digital converter 21 converts the signals into digital values (i.e. coefficients), see para 0025 and 0038).
As per claim 2, Schrey further discloses the image sensor assembly according to claim 1, wherein the converter circuit comprises a differential analog-to-digital converter (fig. 4, image sensor circuit, analog-to-digital converter 21) configured to convert differential input signals applied between a first converter (fig. 4, image sensor, differential amplifier, input CS1) input and second converter (fig. 4, image sensor, differential amplifier, input CS2) input into the digital coefficients, and wherein each differential input signal results from applying one of the first pixel signals to the first converter input and from applying of the second pixel signals to the second converter input (para 0038).
As per claim 3, Schrey further discloses the image sensor assembly according to claim 1, further comprising:
a switching assembly (fig. 4, image sensor circuit, S1, S2) configured to connect the first converter input (fig. 4, image sensor circuit, differential amplifier, input CS1) with the first pixel output (fig. 4, image sensor circuit, column line) and to disconnect the second converter input (fig. 4, image sensor circuit, differential amplifier, input CS2) from the first pixel output in a first operational state, and to disconnect the first converter input from the first pixel output and to connect the second converter input to the first pixel output in a second operational state (para 0038).
As per claim 5, Schrey further discloses the image sensor assembly according to The image sensor assembly according to wherein the converter circuit is configured to successively receive the at least one first pixel signal and the at least one second pixel signal from the first pixel output (fig. 4, image sensor circuit, switches S1 and S2 are provided for applying read out signals CS1 and CS2), and to store the at least one first pixel signal until the at least one second pixel signal is received and/or to store the at least one first pixel signal until the at least one second pixel signal is received (fig. 4, image sensor circuit, capacitances CS1 and CS2 store signal and reset signals).
As per claim 6, Schrey further discloses the image sensor assembly according to claim 5, further comprising:
a first switch connected between the data signal line and the first converter input (fig. 4, image sensor circuit, signal S1 is connected to column line and input of CS1) and a second switch connected between the data signal line and the second converter input (fig. 4, image sensor circuit, signal S2 is connected to column line and input of CS2).
As per claim 7, Schrey further discloses the image sensor assembly according to claim 1, further comprising:
a second amplification transistor (fig. 4, image sensor circuit, Q2 of adjacent pixel) and a second selection transistor (fig. 4, image sensor circuit, Q3 of adjacent pixel) electrically connected in series and configured to output the second pixel signals at a second pixel output (fig. 4, image sensor circuit, output of the adjacent pixel), when the second selection transistor is on.
As per claim 9, Schrey further discloses the image sensor assembly according to claim 7, wherein a gate of the first selection transistor and a gate of the second selection transistor are connected, wherein the first pixel output is connected to a first data signal line, and wherein the second pixel output is connected to a second data signal line (fig. 4, image sensor circuit, first and second pixel connected and output from first pixel is connected to a first output line (i.e. first data line) and second pixel is connected to a second output line (i.e. second data line), see fig. 4).
As per claim 10, Schrey further discloses the image sensor assembly according to claim 7, wherein a gate of the first amplification transistor and a gate of the second amplification transistor are electrically connected (fig. 4, image sensor circuit, is comprised of multiple pixels and they are all electrically connected, i.e. first and second pixel amplification transistors, para 0045, 1480 by 1920 pixels).
As per claim 13, the image sensor assembly according to claim 7, wherein a gate of the first amplification transistor and a gate of the second amplification transistor are electrically disconnected (fig. 4, image sensor circuit, is comprised of multiple pixels, which can be disconnected by powering down the image sensor, i.e. first and second pixel amplification transistors, para 0045, 1480 by 1920 pixels).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Schrey et al (US 2009/0251579 A1) in view of Henderson et al (US 2002/0051067 A1).
As per claim 4, the image sensor assembly according to claim 1, further comprising:
a switching assembly configured to successively pass a first pixel signal and/or a second pixel signal of the first and second pixel signals to each of the first converter input and the second converter input.
Schrey fails to teach the limitations as recited above in claim 4. However, Henderson discloses a solid-state image sensor for reducing noise comprising a chopper circuit 336 for passing a first pixel signal and/or a second pixel signal to a first converter input VSIG and a second converter input VBCK (Henderson, fig. 7, pixel 300, column circuit 332, para 0037, 0038, and 0045).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Schrey in view of Henderson as a whole, by incorporating the chopper circuit as taught by Henderson, into the image sensor circuit as taught by Schrey, because doing so would provide a more efficient way of controlling pixel signals, thus reducing the noise of the image sensor.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Schrey et al (US 2009/0251579 A1) in view of Kawahito (US 8,553,112 B2).
As per claim 14, the image sensor assembly according to claim 7, further comprising:
a seventh switch connected directly between the first converter input and the second converter input.
Schrey fails to teach the limitations as recited above in claim 14. However, Kawahito discloses an A/D converter comprising a switch 43 connected directly between inputs 21a and 21b of the A/D converter 11b (Kawahito, fig. 6, A/D converter 11b, switch 43).
Therefore, it would have been obvious to one of ordinary skill in the art, to combine the teachings of Schrey in view of Kawahito as a whole, by incorporating the switch as taught by Kawahito, into the image sensor as taught by Schrey, because doing so would provide a more efficient way of controlling the data within the A/D converter, thus not overloading the image sensor circuit.
As per claim 15, the image sensor assembly according to claim 1, further comprising:
an evaluation unit configured to obtain a digital signal value on the basis of the digital coefficients.
Schrey fails to teach the limitations as recited above in claim 14. However, Kawahito discloses an A/D converter comprising a A/D converter circuit 18 which is connected to an output of the A/D converter circuit 17 which evaluates the number of times the first value appears (Kawahito, fig. 1, A/D converter 11, A/D converter circuit 18, col. 7 lines 42-45).
Therefore, it would have been obvious to one of ordinary skill in the art, to combine the teachings of Schrey in view of Kawahito as a whole, by incorporating the A/D circuit as taught by Kawahito, into the image sensor as taught by Schrey, because doing so would provide a more efficient way of controlling the data within the A/D converter, thus not overloading the image sensor circuit.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Schrey et al (US 2009/0251579 A1) in view of Kobayashi (US 2011/0316635 A1).
As per claim 8, the image sensor assembly according to claim 7,
wherein the first amplification transistor and the second amplification transistor have a same threshold voltage.
However, Kobayashi discloses a amplifier 64 wherein a first and second amplification transistor (Q1 and Q2) may have equal thresholds (Kobayashi, fig. 8, amplifier 64, first and second amplifying transistor Q1 and Q2, para 0046).
Therefore, it would have been obvious to one of ordinary skill in the art, to combine the teachings of Schrey in view of Kobayashi as a whole, by incorporating the amplifier as taught by Kobayashi, into the image sensor as taught by Schrey, because doing so would provide a more efficient way amplifying pixel signal, thus increasing the sensitivity of image sensor.
Allowable Subject Matter
Claims 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, none of the prior art cited alone or in combination provides the motivation to teach the following claimed limitations, with emphasis that it is each claim, taken as a whole, including the interrelationships and interconnections between various claimed elements make them allowable over the prior art of record, the image sensor assembly according to claim 7, further comprising: a third switch connected between the first data signal line and the first converter input, a fourth switch connected between the second data signal line and the second converter input, a fifth switch connected between the first data signal line and the second converter input, and a sixth switch connected between the second data signal line and the first converter input.
Regarding claim 12, claim depend from claim 11 and is allowable for the same reasons stated above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN H MOREHEAD III whose telephone number is (571)270-3845. The examiner can normally be reached M - F 0930-1800 EST.
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/JOHN H MOREHEAD III/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639