DETAILED ACTION
Allowable Subject Matter
Claims 1, 2, 4-9, and 11-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the whole application meets all formal and substantive requirements and that the language of the claims is enabled by, and finds adequate descriptive support in, the application disclosure as originally filed.
Concerning 35 U.S.C. § 102 and §103 requirements, the application meets all requirements. The known prior art does not teach claim 1 as a whole, in particular:
a second voltage-controlled delayer, identical to a first voltage-controlled delayer in the phase-locked loop in structure, wherein the second voltage-controlled delayer is configured to delay, under excitation of the control voltage that is outputted by a filter in the phase-locked loop, the original PWM signal in phase by preset delay duration to obtain a to-be-superimposed signal; and
a logic controller, configured to superimpose the to-be-superimposed signal with the original PWM signal to generate a target PWM signal, wherein a pulse width of the target PWM signal is a sum of the pulse width of the original PWM signal and the preset delay duration;
wherein the preset delay duration is equal to an integer multiple of 1/N, which ranges from 1/N to N/N, of the period of the clock signal, and N is a preset positive integer.
None of the prior art on record contains such a limitation, nor given the prior art on record is it obvious to one ordinarily skilled in the art to add said limitations as recited in claim 1.
In addition, regarding independent claim 8, the known prior art does not teach claim 8 as a whole, in particular:
a second voltage-controlled delayer, identical to a first voltage-controlled delayer in the phase-locked loop in structure, wherein the second voltage-controlled delayer is configured to delay, under excitation of the control voltage that is outputted by a filter in the phase-locked loop, the original PWM signal in phase by preset delay duration to obtain a to-be-superimposed signal; and
a logic controller, configured to superimpose the to-be-superimposed signal with the original PWM signal to generate a target PWM signal, wherein a pulse width of the target PWM signal is a sum of the pulse width of the original PWM signal and the preset delay duration;
wherein the preset delay duration is equal to an integer multiple of 1/N, which ranges from 1/N to N/N, of the period of the clock signal, and N is a preset positive integer.
None of the prior art on record contains such a limitation, nor given the prior art on record is it obvious to one ordinarily skilled in the art to add said limitations as recited in claim 8.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation “the phase-locked loop is a delay-locked loop (DLL)” does not make sense because a PLL and a DLL are separate categories of circuits that contain mutually exclusive components. For example, a PLL uses a VCO to generate a variable frequency, whereas a DLL uses a variable delay line, able to only perform phase alignment, not frequency multiplication. It is unclear how applicant expects a PLL to turn into a DLL.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D HOUSTON whose telephone number is (571)270-3901. The examiner can normally be reached M-F 10-7 CST.
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/ADAM D HOUSTON/ Primary Examiner, Art Unit 2842