DETAILED ACTION
This Office action is in response to the application filed on 23 September 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to argument
Applicant's arguments, see pg. 7-8, filed on 20 July 2026, with respect to the rejection of claim 1 have been fully considered but they are not persuasive. In response to applicant’s argument, “Lakshmanan instead describes a conventional SRF-PLL for grid phase…………The cited disclosure does not teach the claimed ac voltage-control-loop architecture in which the processed ac voltage error is the basis for determining the synchronization angle.”, it is noted that argument about the processed ac voltage error is arguing a limitation from the spec (Form paragraph 7.37.08).
With respect to claim 8, Applicant’s argument, see pg. 8-9, filed on 20 July 2026, regarding the rejection over Lennart (IEEE Journal of Emerging and Selected Topics in Power Electronics ,Volume: 9, Issue: 5) have been considered and are persuasive. That is, Lennart does not reasonably teach that the first-axis component of the current reference is formed as the sum of the claimed processed ac voltage error and the active-power producing current reference.
Claims 9-10 each depend, either directly or indirectly, from claim 8 and are therefore allowable for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lakshmanan.S.A et. al (2015 IEEE Power & Energy Society General Meeting; hereafter “Laksh”).
-Regarding claim 1:
Laksh discloses:
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A method of determining a synchronizing angle for a processing plane (in Sec. I; “phase angle Ө is tracked by synchronizing the voltage space vector”) comprising a first axis and a second axis (in Sec. II; “q or d axis in the Synchronous Reference Frame (SRF)”), the method being performed in a controller that controls a voltage source converter having an alternating current, ac, side and a direct current, dc, side (in abstract; “The energy transfer between Power Electronic Converters (PEC) and grid is improved by proper design of synchronization techniques. Phase Lock Loop (PLL) is used to estimate the grid phase angle.”, where the PEC usually includes ac and dc sides), the method including processing an ac voltage error (Ed - Eref), which ac voltage error (Ed - Eref) is the error of a voltage component (Ed) along the first axis of an ac voltage (E) (in Sec. II; the voltage space vector is synchronized with the q-axis and carrying out the transformation Vqd=TqdVαβ”) at the ac side of the voltage source converter (in abstract; “PEC”), to thereby obtain a processed ac voltage error (iaref) (in Sec II; “Vmcosẟ, here ẟ=Ө-Өest”) the processing of the ac voltage error (Ed - Eref) being processing in a feedback loop (in abstract; “Phase Lock Loop”) used to control the ac voltage at the ac side of the voltage source converter (in abstract; “PEC”), and determining the synchronization angle (in Sec. II; “three-phase abc-frame voltage signal Egabc as the input, and gives the estimated magnitude Vest.mag, frequency fest and phase angle Өest as the output.”) for the processing plane based on the processed ac voltage error (iaref) (in Sec II; “Vmcosẟ, here ẟ=Ө-Өest”).
-Regarding claim 11:
Laksh discloses:
A controller (Fig. 1; SRF PLL) for controlling a voltage source converter having an alternating current, ac, side and a direct current, dc, side (in Sec. I; “the grid connected solar systems will provide the power to fill the demand-supply gap. The Power Electric Converter (PEC) and advanced control techniques are used in power conditioning systems of various applications”, where the solar system usually includes ac and dc sides), the controller being configured to: process an ac voltage error (Ed - Eref), which ac voltage error (Ed - Eref) is the error of a voltage component (Ed) along a first axis of an ac voltage (E) (in Sec. II; the voltage space vector is synchronized with the q-axis and carrying out the transformation Vqd=TqdVαβ”) at the ac side of the voltage source converter, the processing of the ac voltage error (Ed - Eref) being processing in a feedback loop (in abstract; “Phase Lock Loop”) used to control the ac voltage at the ac side of the voltage source converter, where the first axis is an axis of a processing plane also comprising a second axis (in Sec. II; ”q or d axis in the SRF”) and determine a synchronization angle (in Sec. II; “three-phase abc-frame voltage signal Egabc as the input, and gives the estimated magnitude Vest.mag, frequency fest and phase angle Өest as the output.”) for the processing plane based on the processed ac voltage error(iaref) (in Sec II; “Vmcosẟ, here ẟ=Ө-Өest”).
-Regarding claim 14:
Laksh discloses:
A system computer program for determining a synchronizing angle for a processing plane (in Sec. I; “phase angle Ө is tracked by synchronizing the voltage space vector”) having a first axis and a second axis (in Sec. II; “q or d axis in the Synchronous Reference Frame (SRF)”), which synchronization angle is used by a controller comprising a processor and configured to control a voltage source converter, the system being configured to implement [[the]]an operation when being operated on by the processor of the controller the system comprising: the processor, which corresponds to a physical process; (in abstract; “The energy transfer between Power Electronic Converters (PEC) and grid is improved by proper design of synchronization techniques. Phase Lock Loop (PLL) is used to estimate the grid phase angle.”, where the PEC usually includes ac and dc sides) and physical memory comprising computer-executable instructions that, when enacted by the processor, cause the processor to: process an ac voltage error (Ed - Eref), which ac voltage error (Ed - Eref) is the error of a voltage component (Ed) along a first axis of an ac voltage (E) (in Sec. II; the voltage space vector is synchronized with the q-axis and carrying out the transformation Vqd=TqdVαβ”) at [[the]]an ac side of the voltage source converter (in abstract; “PEC”), the processing of the ac voltage error (Ed - Eref) being processing in a feedback loop (in abstract; “Phase Lock Loop”) used to control the ac voltage at the ac side of the voltage source converter (in abstract; “PEC”), where the first axis is an axis of a processing-plane also comprising a second axis (in Sec. II; “q or d axis in the Synchronous Reference Frame (SRF)”); and determine a synchronization angle (6) (in Sec. II; “three-phase abc-frame voltage signal Egabc as the input, and gives the estimated magnitude Vest.mag, frequency fest and phase angle Өest as the output.”) for the processing plane based on the processed ac voltage error (in Sec II; “Vmcosẟ, here ẟ=Ө-Өest”).
-Regarding claim 15:
Laksh discloses:
A non-transitory computer-readable medium having instructions recorded thereon that, when enacted by a computer processor, cause the computer processor to determine a synchronizing angle for a processing plane (in Sec. I; “phase angle Ө is tracked by synchronizing the voltage space vector”) comprising a first axis and a second axis (in Sec. II; “q or d axis in the Synchronous Reference Frame (SRF)”), the instructions causing the computer processor to process an ac voltage error (Ed - Eref), which ac voltage error (Ed - Eref) is the error of a voltage component (Ed) along a first axis of an ac voltage (E) (in Sec. II; the voltage space vector is synchronized with the q-axis and carrying out the transformation Vqd=TqdVαβ”) at [[the]]an ac side of [[the]]a voltage source converter (in abstract; “PEC”), the processing of the ac voltage error (Ed - Eref) being processing in a feedback loop (in abstract; “Phase Lock Loop”) used to control the ac voltage at the ac side of the voltage source converter (in abstract; “PEC”), where the first axis is an axis of a processing-plane also comprising a second axis (in Sec. II; “q or d axis in the Synchronous Reference Frame (SRF)”) and determine a synchronization angle (6) (in Sec. II; “three-phase abc-frame voltage signal Egabc as the input, and gives the estimated magnitude Vest.mag, frequency fest and phase angle Өest as the output.”) for the processing plane based on the processed ac voltage error (in Sec II; “Vmcosẟ, here ẟ=Ө-Өest”).
-Regarding claim 2:
Laksh discloses:
The method as claimed in claim 1, wherein the processing in the feedback loop comprises regulating the ac voltage error (Ed - Eref) down to zero (in Sec. II; “PI controller is considered as loop filter and gains of the loop filter is then designed so that Vd follows the Vdref =0. If Vd = 0 then the space voltage vector is synchronized along the q-axis and the estimated frequency ωest is locked on the system frequency ω.”).
-Regarding claim 3:
Laksh discloses:
The method according to claim 2, wherein the ac voltage error (Ed - Eref) is formed as a difference between said voltage component (Ed) along the first axis (in Sec. II; “the voltage space vector is synchronized with the q-axis and carrying out the transformation Vqd=TqdVαβ”) and a reference voltage (Eref), which reference voltage (Eref) is separate from zero.
-Regarding claim 4:
Laksh discloses:
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The method according to claim 1, wherein the determining of the synchronization angle (6) comprises applying proportional control (KE) on the processed ac voltage error for obtaining an angular velocity (ωp) (Fig. 2; PI controller provides κ and ωest, where κ includes proportional control and ωest is the angular velocity).
-Regarding claim 5:
Laksh discloses:
The method as claimed in claim 4, wherein the determining of the synchronization angle (6) comprises combining the obtained angular velocity (Wp) with a nominal angular velocity (wi) (in Sec. II; “The estimated frequency ωest is the sum of the loop filter output and the feed forward frequency ωff.”)
-Regarding claim 6:
Laksh discloses:
The method as claimed in claim 5, wherein the determining of the synchronization angle (6) comprises integrating the angular velocity combination (w, + wp) in order to obtain the synchronization angle (in Sec. II; phase angle θ is estimated with θest which is the integral of the estimated frequency ωest.”, where ωest is an angular velocity not frequency. It is a typo in the prior art).
-Regarding claim 7:
Laksh discloses:
The method according to any previous claim 1,further comprising obtaining the ac voltage (Es) at the ac side of the voltage source converter, determining a reference voltage (vref) for the voltage source converter, where the ac side voltage is obtained in a control plane and the reference voltage is determined in the processing plane, transforming the ac side voltage from the control plane to the processing plane using the synchronization angle (6) and transforming the reference voltage from the processing plane to the control plane using the synchronization angle (6) (in Sec. II; “In this system, Egabc is transformed into the stationary reference frame as Vαβ then Vαβ is further transformed into the synchronous dq-frame as Vdq using park and Clarke transformation matrices.”).
-Regarding claim 12:
Laksh discloses:
The controller according to claim 11, wherein the controller is a power synchronization controller that is mapped onto a vector current control structure (in Sec. 1; “PLL is used to synchronizing the utility voltage and controlled currents or voltages in utility interface of PEC.”).
-Regarding claim 13:
Laksh discloses:
A converting arrangement comprising a voltage source converter and a controller configured to process an ac voltage error (Ed - Ere), which ac voltage error (Ed - Eref) is the error of a voltage component along a first axis of an ac voltage (in Sec. II; the voltage space vector is synchronized with the q-axis and carrying out the transformation Vqd=TqdVαβ”) at the ac side of the voltage source converter, the processing of the ac voltage error (Ed- Eref) being processing in a feedback loop (in abstract; “Phase Lock Loop”) used to control the ac voltage at the ac side of the voltage source converter, where the first axis is an axis of a processing plane also comprising a second axis and determine a synchronization angle for the processing plane (in Sec. II; ”q or d axis in the Synchronous Reference Frame (SRF)”) based on the processed ac voltage error (iaref) (in Sec II; “Vmcosẟ, here ẟ=Ө-Өest”).
Allowable Subject Matter
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
The following is a statement of reasons for the indication of allowable subject matter:
-with respect to claim 8:
the prior art in Laksh discloses the claimed invention in basic claims but do not further disclose that the determining of the current reference includes determining a component of the current reference along the first axis as a sum of the processed ac voltage error and an active-power- producing current reference.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET.
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/SEUNG HO CHOI/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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