Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (US 20200020384 A1).
Regarding claims 1, 10, and 19: Zhao discloses a memory system (200, FIG. 2), comprising: dynamic random-access memory (DRAM) (par. 1-2, 34-36) comprising a plurality of DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks (groups of DRAM banks such as paired banks, par. 56); and a memory controller (292, FIG. 2) for managing the DRAM, the memory controller comprising: a request scheduler (of controller 510: 512, 520, 538, 514, 530, FIG. 5) configured to receive memory transactions and send memory request commands to the DRAM banks; and a refresh scheduler (of controller 510: 514, 532, 538, FIG. 5; 700, FIG. 7) configured to: monitor a status of a dynamically changing refresh requirement for the DRAM; determine an alert level for the DRAM based at least in part on a duration of time until a hard refresh deadline (alert level corresponding to priority status of banks based on counter 730, par. 46; hard deadline corresponding to enforced timing commands such as refreshes based on JEDEC specification, which involves mandatory refreshes within a certain time across DRAM cells, par. 36); and manage, based on the determined alert level, the DRAM banks to which refresh commands are sent and the memory transactions for which memory request commands are sent by the request scheduler (memory access requests and refresh commands managed to banks based on priority, par. 46).
Regarding claims 2, 11, and 20: Zhao discloses a memory system (200, FIG. 2), wherein the duration of time until a hard refresh deadline comprises a deadline by which all DRAM banks of the DRAM must be refreshed (hard deadline corresponding to enforced timing commands such as refreshes based on JEDEC specification, which involves mandatory refreshes within a certain time across DRAM cells, par. 36).
Regarding claims 3 and 12: Zhao discloses a memory system (200, FIG. 2), wherein the refresh scheduler is configured to manage the DRAM banks (par. 43) to which refresh commands are sent and the memory transactions for which memory request commands are sent by the request scheduler based further on a priority value (priority status of the refresh command based on an urgent refresh count threshold, par. 46) for each memory transaction.
Regarding claims 4 and 13: Zhao discloses a memory system (200, FIG. 2), wherein the refresh scheduler is configured to manage the DRAM banks to which refresh commands are sent based on a combination of the determined alert level (refresh commands selected taking into account priority status and…, par. 43) and a status of each DRAM bank (… page status of banks in memory, par. 43).
Regarding claims 5 and 14: Zhao discloses a memory system (200, FIG. 2), wherein the status of each DRAM bank comprises an indication of whether the DRAM bank is open or closed (banks either open, par. 39, or closed, par. 42).
Regarding claims 6 and 15: Zhao discloses a memory system (200, FIG. 2), wherein the refresh scheduler is configured to manage the DRAM banks to which refresh commands are sent based further on a priority value (priority status of the refresh command based on an urgent refresh count threshold, par. 46) for memory transactions for each DRAM bank.
Regarding claims 7 and 16: Zhao discloses a memory system (200, FIG. 2), wherein the refresh scheduler is configured to manage the DRAM banks to which refresh commands are sent by proactively sending precharge commands (par. 56) to DRAM banks based on a combination of the determined alert level and a status of the DRAM banks (priority status and page status, par. 43).
Regarding claims 8 and 17: Zhao discloses a memory system (200, FIG. 2), wherein the refresh scheduler is configured to manage the memory transactions for which memory request commands are sent by the request scheduler (memory requests, par. 43) based on a combination of the determined alert level (priority status, par. 43) and a type of memory request command (type of memory access, par. 45) to be sent to each DRAM bank for which a memory transaction has been received.
Regarding claims 9 and 18: Zhao discloses a memory system (200, FIG. 2), herein the refresh scheduler is configured to (i) block activate (ACT) commands for non-priority memory transactions (commands are prioritized for more urgent refresh commands, par. 46-48, 57) for a first alert level (intermediate priority, par. 46, FIG. 7) and (ii) block all ACT commands and column read or write (COL) commands (block activation or row of corresponding bank, includes ACT and COL commands, par. 52) for memory transactions for a second alert level (urgent priority, par. 46, FIG. 7) that is higher than the first alert level.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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