DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225.
In regards to claim 1: Miike teaches a clock architecture (figure 12), the clock architecture comprising one or more clock module layer (figure 12); each clock module layer comprising one or more clock module (102, 116, 144 and buffers 105) (second module is 103, 114, 146, 109), each clock module comprising an internal clock (output of PLL 102), a selection switch circuit (144 and first buffer of 105) and a plurality of clock buffer circuits (105); wherein the internal clock is configured to generate a local clock signal (PTOUT); a first input terminal of the selection switch circuit receives the local clock signal (top input to mux 144), a second input terminal of the selection switch circuit receives an external clock signal (external clock CLKT is fed to the bottom input of mux 144), a plurality of output terminals (top output to top buffer of 105 and bottom output top bottom buffer of 105) of the selection switch circuit (144 and first buffer of 105) are respectively connected to input terminals of the plurality of clock buffer circuits (top buffer of 105 and bottom buffer of 105), and an enable terminal (arrow down into mux 144) of the selection switch circuit (144 and first buffer) is configured to receive an enable signal (DLLE [0067] “a PLL enable signal DLLE”); and the selection switch circuit (144 and first buffer) is configured to enable, all the output terminals to output the local clock (when PTOUT is selected) or enable all the output terminals to output the external clock signal (when CLKT is selected), according to the enable signal (DLLE). Miike does not teach the internal local clock is an independently generated local clock. Lilja et al teaches the options of either a global external clock (figure 1B) or independent local clocks ([0083] “In other words, in this example, the cell array conforms to the “Poly Local” technique described herein such that the device does not utilize any form of a centralized clock distribution network to distribute clocks to the cells but instead each cell has its own local clock generator to independently generate a local clock without synchronization with other local clocks. This arrangement may reduce the delivery time of clock signals to the local cell(s) and reduce the circuitry for delivering clock signals” figure 1A) each with its own advantages but teaches these two clock sources as alternate embodiments of the invention instead of a selection between the two. It would have been obvious to have an independent local clock generator as a clock source because this would have allowed asynchronous processing ([0006] “In other examples, the techniques allow local clocks to be independently generated, thus allowing splitting of clock domains within an integrated circuit or electronic system at a very fine level, e.g., down to the level of a handful of gates if desired”).
In regards to claim 16: all outputs of the selection switch circuit (144 and first buffer of 105) are switched to either the external clock or local clock simultaneously in that they are all branched off the same line before the first buffer 105).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225 as applied to claim 1 above, and further in view of Garde PN 5,922,076.
In regards to claim 2: Neither Miike nor Lilja et al state the source of the external/global clock being a host clock. Garde teaches selecting a local clock LCLK and an external Host clock HCLK using a switching element MUX 124. It would have been obvious to have the external clock be a clock from a host because hosts are common sources for clocks.
Claim(s) 3-4, 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225 as applied to claim 1 above, and further in view of Sawtell PN 5,227,672.
In regards to claim 3: Miike teaches each output of the clock buffers being connected to next stage modules but does not state next stage modules are clock modules at a next clock module layer. While the examiner recognizes the claim language is in the alternative “non-clock module and/or clock module” thus Sawtell is extraneous. Sawtell is being cited for teaching both alternatives. Sawtell teaches (figure 6) an external clock 502 and in internal clock generator connected to a clock selecting device (clock changeover 514) that can output either the external clock or the internal clock to either a non-clock module (power converter 516) and/or to a clock module 520 with its own internal clock generator 522. It would have been obvious to daisy chain the clock modules because this would have allowed for multiple levels of clock selection control.
In regards to claim 4: Claim 4 is a conditional claim requiring the second option of the or statement “when the next-stage module is the clock module”, Thus Sawtell is also extraneous for claim 4. Sawtell however teaches one of the inputs of the clock selector (524) is one of the outputs of the previous stage clock selector (514). Miike teaches the claimed buffers.
In regards to claim 7: Sawtell teaches the non-clock module is a “device 308 which uses the output clock signal from clock changeover device 320” but is totally silent upon the type of device. Only that it is a device that uses a clock. Miike however teaches the device may be a register which is a storage module, a logic circuit which is a computing module, “supplied to internal circuit such as CPU” (figure 16) which is also a computing module. Lilja et al teaches the clocked device is a “processing module” (figures 1A and 1B).
In regards to claim 8: Lilja et al teaches ([0045] “In general, each stochastic processing module 10 represents a functional component, e.g., computational unit, designed to perform operations, such as arithmetic operations, image processing, signal processing, field-programmable gate arrays (FPGAs), parallel data processing, convolutional neural networks, speech processing, sensors and the like. Each stochastic processing module 10 may include logic gates, memory units, multiplexers, or other devices that processes input information and generates output information”).
Claim(s) 5-6, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225 as applied to claim 1 above, and further in view of Tsai et al PN 2021/0311889 and Nguyen PN 2009/0031051.
In regards to claim 5: Miike does not teach the source of the enable/selection signal being a baseboard management controller. Tsai et al teaches a baseboard management controller causing a I/O expander to generate a SEL signal to select a reference clock source from RefClk #0 and RefCLK #1. In Tsai et al the BMC in the host instead of in the connected module (such as Miike’s clock module). It would have been obvious to have a BMC control the selection/enable signal to select the clock source because this would have allowed for an intelligent intermediary between the server hardware and a processor core. Nguyen teaches a host controlling plural BMC’s (204) wherein each BMC is in the connected module (S1-Sn). It would have been obvious to have the BMC be in the connected clock module because this would have made the BMC be proximate to the circuits it controls.
In regards to claim 6: Nguyen teaches a HUB 201, physical layers ([0021] “The USB specification totally defines the physical layer, protocol layer, transfer model, power distribution, mechanical, hub operation of a USB systems”), network ports (200(1) to 200(n)) connected to interfaces of the host ([0006] “The Universal Serial Bus (USB) is a peripheral bus specification that supports data exchange between a host computer and a wide range of simultaneously accessible peripherals. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. The capability eliminates the need to install interface card into dedicated computer slots and reconfigure the system each time a peripheral is attached or detached from a PC. Computer peripheral input/output (I/O) devices connect to a variety of data ports or external connectors of a host computer system, which includes a system processor and memory”).
In regards to claim 19: Miike teaches a clock architecture (figure 12), the clock architecture comprising one or more clock module layer (figure 12); each clock module layer comprising one or more clock module (102, 116, 144 and buffers 105) (second module is 103, 114, 146, 109), each clock module comprising an internal clock (output of PLL 102), a selection switch circuit (144 and first buffer of 105) and a plurality of clock buffer circuits (105); wherein the internal clock is configured to generate a local clock signal (PTOUT); a first input terminal of the selection switch circuit receives the local clock signal (top input to mux 144), a second input terminal of the selection switch circuit receives an external clock signal (external clock CLKT is fed to the bottom input of mux 144), a plurality of output terminals (top output to top buffer of 105 and bottom output top bottom buffer of 105) of the selection switch circuit (144 and first buffer of 105) are respectively connected to input terminals of the plurality of clock buffer circuits (top buffer of 105 and bottom buffer of 105), and an enable terminal (arrow down into mux 144) of the selection switch circuit (144 and first buffer) is configured to receive an enable signal (DLLE [0067] “a PLL enable signal DLLE”); and the selection switch circuit (144 and first buffer) is configured to enable, all the output terminals to output the local clock (when PTOUT is selected) or enable all the output terminals to output the external clock signal (when CLKT is selected), according to the enable signal (DLLE). Miike does not teach the internal local clock is an independently generated local clock. Lilja et al teaches the options of either a global external clock (figure 1B) or independent local clocks ([0083] “In other words, in this example, the cell array conforms to the “Poly Local” technique described herein such that the device does not utilize any form of a centralized clock distribution network to distribute clocks to the cells but instead each cell has its own local clock generator to independently generate a local clock without synchronization with other local clocks. This arrangement may reduce the delivery time of clock signals to the local cell(s) and reduce the circuitry for delivering clock signals” figure 1A) each with its own advantages but teaches these two clock sources as alternate embodiments of the invention instead of a selection between the two. It would have been obvious to have an independent local clock generator as a clock source because this would have allowed asynchronous processing ([0006] “In other examples, the techniques allow local clocks to be independently generated, thus allowing splitting of clock domains within an integrated circuit or electronic system at a very fine level, e.g., down to the level of a handful of gates if desired”). Tsai et al teaches a clock from a host server RefClk #0. Miike teaches plural non-clock modules (121, 122).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225 and Sawtell PN 5,227,672 as applied to claim 7 above, and further in view of Takano et al PN 5,631,931.
In regards to claim 9: Sawtell teaches the clocked unit is a “device” without limiting the type of device. Takano et al teaches a communication card in a slot that receives a selected clock (Abstract “Each communication card includes a clock supplying section including a frequency divider for extracting a clock from the transmission lines and a tri-state device outputting the clock to the clock bus; a clock receiving section including a clock selector for selecting one clock from a plurality of the bus-type clock lines, and a frequency multiplier for multiplying the frequency of the selected clock” Column 2 line 8 et. seq. “This communication card 14 is so constructed that the clock receiving section receiving the clock from the NCLK 19 selects the reference clock, which is either one of two sorts of the act system/standby system, through the clock monitoring and controlling circuit 13”. It would have been obvious to allow the device to be a communication device because this would have prevented limiting the types of devices that can be clocked.
In regards to claim 10: Takano et al teaches a communication card in a slot that selects a clock. Sawtell teaches daisy chained clock modules. It would have been obvious to have the clock module that sends the clock to the next layer be a communication card in a slot because this is a form of device that sends communications.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225, Tsai et al PN 2021/0311889 and Nguyen PN 2009/0031051 as applied to claim 5 above, and further in view of Lee PN 2006/-2-9680.
In regards to claim 15: Tsai et al teaches a BMC sending a signal to select the clock but never mentions the standard GPIO pins of a BMC is used for sending this selection signal. Lee teaches ([0028] “Another end of the selection switch unit 20 is connected to the baseboard management controller 30 through the GPIO pins and SM bus. The selection switch unit 20 is a multiplexer that consists of MOS transistor switches or IC route switches. When the selection switch unit 20 receives the selection switch signal from the baseboard management controller 30 through the GPIO pins, a route switch operation is executed to select the first network port 10 or the second network port 11 to transmit data”). It would have been obvious to use a BMC’s standard GPIO pins to send the select signal because this would have prevented having to redesign a BMC to create a separate I/O port that is not the standard GPIO pins included in a standard BMC for the selecting signal.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225 and Sawtell PN 5,227,672 as applied to claim 8 above, and further in view of Seo et al PN 2001/0056580.
In regards to claim 17: Lilja et al teaches a memory units but is silent on the form the storage unit may take. Seo et al teaches ([0006] “a storage unit 4 such as a hard disk or memory banks for storing the extracted PL data”).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miike PN 2007/0273410 in view of Lilja et al PN 2017/0255225, Tsai et al PN 2021/0311889 and Nguyen PN 2009/0031051as applied to claim 19 above, and further in view of Takano et al PN 5,631,931.
In regards to claim 20: Miike teaches clocking registers, Lilja et al teaches clocking processors. Neither expressly teaches clocking a communication module. Takano et al teaches a communication card in a slot that receives a selected clock (Abstract “Each communication card includes a clock supplying section including a frequency divider for extracting a clock from the transmission lines and a tri-state device outputting the clock to the clock bus; a clock receiving section including a clock selector for selecting one clock from a plurality of the bus-type clock lines, and a frequency multiplier for multiplying the frequency of the selected clock” Column 2 line 8 et. seq. “This communication card 14 is so constructed that the clock receiving section receiving the clock from the NCLK 19 selects the reference clock, which is either one of two sorts of the act system/standby system, through the clock monitoring and controlling circuit 13”. It would have been obvious to have the clock module that sends the clock to the next layer be a communication card in a slot because this is a form of device that sends communications.
Allowable Subject Matter
Claims 11-14, 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 11: The examiner found no references that taught limiting the number of clock module layers based on a maximum clock jitter limit. Most talked about the maximum amount of jitter allowed per module and limiting the jitter. While the inverse does make a logical sense the examiner found no references that expressly limited the number of clock modules based on jitter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Multiple references are cited that teach selecting between clocks using a switch/mux.
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/Paul R. MYERS/ Primary Examiner, Art Unit 2176
Prosecution Insights