Prosecution Insights
Last updated: August 16, 2026
Application No. 18/850,596

COVERLAY FILM, PRINTED WIRING BOARD, METHOD FOR MANUFACTURING COVERLAY FILM, AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

Non-Final OA §102
Filed
Sep 25, 2024
Priority
Mar 31, 2022 — JP 2022-059505 +1 more
Examiner
PATEL, AMOL H
Art Unit
Tech Center
Assignee
Sumitomo Electric Industries Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
549 granted / 642 resolved
+25.5% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
16 currently pending
Career history
652
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.1%
+13.1% vs TC avg
§102
35.8%
-4.2% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 642 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsiang et al. (TW200920207A). As to claim 1, Hsiang discloses a coverlay film (figs. 1A-1C) comprising: an insulating film 110 having a first main surface and a second main surface as a surface opposite to the first main surface; an adhesive layer 112 disposed on the first main surface and formed from an uncured adhesive; and a separator 114 disposed on the adhesive layer, wherein the insulating film has a thickness of more than or equal to 2 µm and less than or equal to 15 µm (¶0018), and the adhesive layer has a thickness of more than or equal to 10 µm and less than or equal to 50 µm (¶0020). As to claim 2, Hsiang discloses a protective film 118, wherein the protective film is disposed on the second main surface (figs. 1A-1B). As to claim 3, Hsiang discloses that a peel strength of the protective film with respect to the insulating film is greater than a peel strength of the separator with respect to the adhesive layer (¶0011). As to claim 4, Hsiang disclsoes that the thickness of the adhesive layer is larger than the thickness of the insulating film (¶0018-0020). As to claim 5, Hsiang disclsoes that the insulating film has a thickness of more than or equal to 2 µm and less than or equal to 13 µm, and the adhesive layer has a thickness of more than or equal to 20 µm and less than or equal to 50 µm (¶0018-0020). As to claim 6, Hsiang discloses that the insulating film is formed from polyimide or a liquid crystal polymer (¶0019). As to claim 7, Hsiang discloses a printed wiring board 120 comprising: a base film having a third main surface (figs. 1B-1C); a conductive pattern disposed on the third main surface (¶0003 discloses a PI substrate and a copper foil metal layer); and the coverlay film according to claim 1, wherein the separator is peeled off in the coverlay film, the coverlay film is disposed on the third main surface such that the adhesive layer covers the conductive pattern, and the adhesive is cured (figs. 1A-1C). As to claim 8, Hsiang discloses a method for manufacturing a coverlay film (figs. 1A-1C), the method comprising: preparing an insulating film 110 which has a first main surface and a second main surface as a surface opposite to the first main surface, and in which a protective film 118 is disposed on the second main surface; forming an adhesive layer 112 from an uncured adhesive on the first main surface; and disposing a separator 114 on the adhesive layer, wherein the insulating film has a thickness of more than or equal to 2 µm and less than or equal to 15 µm (¶0018), and the adhesive layer has a thickness of more than or equal to 10 µm and less than or equal to 50 µm (¶0020). As to claim 9, Hsiang discloses peeling off the protective film from the insulating film (figs. 1B-1C). As to claim 10, Hsiang discloses a method for manufacturing a printed wiring board, the method comprising: preparing a coverlay film having an insulating film 110 including a first main surface and a second main surface as a surface opposite to the first main surface, an adhesive layer 112 disposed on the first main surface and formed from an uncured adhesive, a protective film 118; disposed on the second main surface, and a separator 114 disposed on the adhesive layer; peeling off the separator from the adhesive layer (fig. 1B); preparing a base film which has a third main surface and in which a conductive pattern is disposed on the third main surface (fig. 1B, see circuit board 120; ¶0003); disposing the coverlay film on the third main surface such that the adhesive layer covers the conductive pattern, and curing the adhesive; and peeling off the protective film from the insulating film (figs. 1B, 1C). As to claim 11, Hsiang discloses that the protective film is peeled off after the coverlay film is disposed on the third main surface (fig. 1C). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (Pub. No. US 2022/0251433) discloses a base substrate having a thickness in the range of 5 to 50μm, an adhesive layer about 10-50μm thick, and a separator film. Wu et al. (Pub. No. US 2016/0205776) discloses an insulation film, an adhesive layer, and a release film. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMOL H PATEL whose telephone number is (571)270-7833. The examiner can normally be reached 9:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY THOMPSON can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMOL H PATEL/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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Prosecution Timeline

Sep 25, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
95%
With Interview (+9.3%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 642 resolved cases by this examiner. Grant probability derived from career allowance rate.

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