DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-15 are objected to because of the following informalities: Claim 1, line 5 and line 8 recite, “the gate”, which should be corrected to “the gate of the switching element” to have proper antecedent basis. Appropriate correction is required. Claims 2-10 and 12-15 depend from objected Claims 1 and 11 respectively.
Claim 11, line 5 and line 8 recite, “the gate”, which should be corrected to “the gate of the switching element” to have proper antecedent basis. Appropriate correction is required. Claims 2-10 and 12-15 depend from objected Claims 1 and 11 respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0140630) in view of Takizawa (US 2017/0207782).
Regarding Claim 1, Chen discloses a drive circuit (Figures 1-4) comprising:
a switching element (comprising 100, Figure 1);
an ON circuit that injects charge into a gate of the switching element according to a drive signal (ON circuit comprising 216, 212, Rgate in 210 injects current a gate of SW-SEN and SW_MAIN in 100, Figure 1), the ON circuit including a first transistor having a first source/drain terminal electrically coupled to the gate and a second source/drain terminal (a first transistor, not shown, with a first source/drain terminal connected to gate of SW-SEN and SW_MAIN in 100, , of drive amplifier 212, Figure 1, Paragraph 33, “…driver circuit 200 may, for example, be fabricated as a low-cost silicon MOSFET that is co-packaged in a module with the GaN die 100”);
a first OFF circuit that extracts charge from the gate of the switching element in response to a drive signal (comprising 216, 212, Rgate in 210, Figure 1), the first OFF circuit including a second transistor having a third source/drain terminal electrically coupled to the gate and a fourth source/drain terminal coupled to a second resistor (a second transistor, not shown, of drive amplifier 212, with a third source/drain terminal connected to gate of SW-SEN and SW_MAIN in 100, Figure 1, Figure 1); and
a second OFF circuit that is different from the first OFF circuit (comprising 230, Figure 1) and extracts charge from the gate of the switching element in response to an overcurrent detection signal (Q1 in 230 receives output of overcurrent/fault detection logic circuit 220 and extracting charge from the gate of SW-SEN and SW_MAIN via Q1, R1, Figure 1, Paragraph 34, “…When the drain voltage sense signal VDSEN reaches or exceeds Vref, the latch outputs a fault signal FLT of a predetermined level, e.g. 5V. The fault signal FLT is passed, via inverter 214 to the gate drive circuitry 210, e.g. as an input to AND gate 216, as shown in FIG. 1. The fault signal FLT is also passed directly to the fast soft turn-off circuitry 230”).
Chen does not show the connection details of the drive amplifier 212, to the second source/drain terminal coupled to a first resistor and the fourth source/drain terminal coupled to a second resistor.
Takizawa discloses driver circuit (Figure 1-7)comprising:
a switching element (2a, 2a’, Figures 1, 5-7);
an ON circuit that injects charge into a gate of the switching element according to a drive signal, the ON circuit including a first transistor having a first source/drain terminal electrically coupled to the gate and a second source/drain terminal connected to first resistor (a first transistor 34 with an emitter terminal connected to the gate of 2a, 2a’ and an emitter terminal connected to resistor 36, Figures 1, 5-7);
a first OFF circuit that extracts charge from the gate of the switching element in response to a drive signal, the first OFF circuit including a second transistor having a third source/drain terminal electrically coupled to the gate and a fourth source/drain terminal coupled to a second resistor (a second transistor 35 with an emitter terminal connected to the gate of 2a, 2a’ and a collector terminal connected to resistor 37, Figures 1, 5-7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the drive circuit of Chen, a first resistor and a second resistor as taught by Takizawa, to control the gate-source voltage of the switching element so that the rising and falling in the gate-source voltage are prevented from becoming excessively abrupt for carrying out the suppression of a surge voltage (see Takizawa, Paragraphs 13 , 67).
Regarding Claim 2, combination of Chen and Takizawa discloses the drive circuit according to Claim 1, wherein when charge is extracted from the gate of the switching element using the second OFF circuit, the ON circuit and the first OFF circuit are set in an OFF state (Chen, Paragraphs 34-35, two-stage turn-off, fast soft-turn-off by second OFF circuit and after a delay hard or full turn-off by the first OFF circuit. “….in first stage of turn-off, the fast soft turn-off circuitry 230 rapidly pulls down the gate of the GaN switch SW_MAIN to a level close to or below the threshold voltage (stage 1, fast soft-turn off). Then, after a planned delay, Vgs is pulled down to a few volts than the threshold voltage (stage 2, full or hard turn-off)”).
Regarding Claim 3, combination of Chen and Takizawa discloses the drive circuit according to Claim 1, wherein a speed of charge extraction from the gate of the switching element by the second OFF circuit is lower than a speed of charge extraction from the gate of the switching element by the first OFF circuit (Chen, Paragraphs 34-35, “….in first stage of turn-off, the fast soft turn-off circuitry 230 rapidly pulls down the gate of the GaN switch SW_MAIN to a level close to or below the threshold voltage (stage 1, fast soft-turn off). Then, after a planned delay, Vgs is pulled down to a few volts than the threshold voltage (stage 2, full or hard turn-off)”, Paragraph 36).
Regarding Claim 4, combination of Chen and Takizawa discloses the drive circuit according to Claim 3, the second OFF circuit is coupled to a third resistor (Chen, comprising R1 in 230, Figure 1), the second resistor controls the speed of charge extraction from the gate of the switching element by the first OFF circuit (Takizawa, Paragraphs 13, 67), and the third resistor controls the speed of charge extraction from the gate of the switching element by the second OFF circuit (Chen, Paragraph 36, “…The values of the resistor R1 of the fast soft turn-off circuitry 230 and the gate resistor Rgate of the gate driver, and the ratio of R1 to Rgate, and other parameters of the gate driver 210 and fast soft turn-off circuitry 230 are selected to control the speed and timing of the first and second stages of switching, and the voltage to which the fast soft turn-off circuit pulls down the gate during the fast soft-switching stage”).
Regarding Claim 5, combination of Chen and Takizawa discloses the drive circuit according to Claim 4, wherein the third resistor has a resistance value larger than a resistance value of the second resistor (Chen’s Paragraph 36, “….The values of the resistor R1 of the fast soft turn-off circuitry 230 and the gate resistor Rgate of the gate driver, and the ratio of R1 to Rgate, and other parameters of the gate driver 210 and fast soft turn-off circuitry 230 are selected to control the speed and timing of the first and second stages of switching, and the voltage to which the fast soft turn-off circuit pulls down the gate during the fast soft-switching stage” in the combination).
Regarding Claim 11, Chen discloses a control method for a drive circuit (Figures 1-4) comprising:
injecting charge into a gate of a switching element in response to an ON signal of an ON circuit (injecting current to gate of SW-SEN and SW_MAIN in 100 using ON circuit comprising 216, 212, Rgate in 210, Figure 1) including a first transistor having a first source/drain terminal electrically coupled to the gate and a second source/drain terminal (a first transistor, not shown, with a first source/drain terminal connected to gate of SW-SEN and SW_MAIN in 100, , of drive amplifier 212, Figure 1, Paragraph 33, “…driver circuit 200 may, for example, be fabricated as a low-cost silicon MOSFET that is co-packaged in a module with the GaN die 100”);
extracting charge from the gate of the switching element in response to an OFF signal of a first OFF circuit (extracting charge from the gate of SW-SEN and SW_MAIN via 216, 212 Rgate in response to an OFF signal at IN during normal operation, Figure 1, Paragraphs 33-34) including a second transistor having a third source/drain terminal electrically coupled to the gate and a fourth source/drain terminal coupled to a second resistor (a second transistor, not shown, of drive amplifier 212, with a third source/drain terminal connected to gate of SW-SEN and SW_MAIN in 100, Figure 1, Figure 1); and
upon detecting an overcurrent detection signal (detecting overcurrent using Rsen and fault detection logic circuit 220, Figure 1), extracting charge from the gate of the switching element through a path, of a second OFF circuit, different from a path from which charge is extracted according to the OFF signal (extracting charge from the gate of SW-SEN and SW_MAIN via Q1, E1 in 230, in response to an OFF signal from the output of 220 to the gate of Q1 in 230, Figure 1, Paragraph 34).
Regarding Claim 12, Chen discloses the control method for the drive circuit according to Claim 11, wherein a speed of charge extraction when an overcurrent is detected is lower than a speed of charge extraction according to the OFF signal (Paragraphs 34-35, “….in first stage of turn-off, the fast soft turn-off circuitry 230 rapidly pulls down the gate of the GaN switch SW_MAIN to a level close to or below the threshold voltage (stage 1, fast soft-turn off). Then, after a planned delay, Vgs is pulled down to a few volts than the threshold voltage (stage 2, full or hard turn-off)”, Paragraph 36).
Claims 6, 10, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0140630) in view of Takizawa (US 2017/0207782) and Nakamori (US 2017/0358982).
Regarding Claim 6, combination of Chen and Takizawa does not specifically disclose the drive circuit according to Claim 1, wherein the ON circuit and the first OFF circuit are invalidated when an overcurrent is detected.
Nakamori discloses a drive circuit (Figures 1-5) comprising:
a switching element (comprising a switching element in 1, Figures 1, 4-5);
an ON circuit that injects charge into a gate of the switching element according to a drive signal (ON circuit comprising 26, 21 injects current a gate of switching element in 1 according to a drive signal CS, Figures 1, 4-5), the ON circuit including a first transistor having a first source/drain terminal electrically coupled to the gate and a second source/drain terminal (comprising transistor 21 having source/drain terminal electrically coupled to the switching element in 1) ;
a first OFF circuit that extracts charge from the gate of the switching element in response to a drive signal (comprising 27, 21 that extracts charge from the gate of the switching element in response to a drive signal CS, Figure 1), the first OFF circuit including a second transistor having a third source/drain terminal electrically coupled to the gate and a fourth source/drain terminal coupled to a second resistor (comprising 27 having a third source/drain terminal electrically coupled to the gate of the switching element and a fourth source/drain terminal coupled to a second resistor 68); and
a second OFF circuit that is different from the first OFF circuit (comprising 61, Figure 1) and extracts charge from the gate of the switching element in response to an overcurrent detection signal (61 receives output of overcurrent/fault detection circuit comprising 22, 23, 24 and extracts charge from the gate of the switching element, Figures 1, 4-5),
wherein the ON circuit and the first OFF circuit are invalidated when an overcurrent is detected (Paragraph 49, “The individual overcurrent detection signal Scu, which has been inverted to the H-level, is supplied to the gate of the P-channel field effect transistor 26 via the OR circuit 28 to cause the P-channel field effect transistor 26 to be non-conductive”, Paragraph 58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the ON circuit and the first OFF circuit in the drive circuit of Chen, to be invalidated when an overcurrent is detected in a phase as taught by Nakamori, such that normal driving operation of the switching element can be halted to protect the switching element from damaging overcurrent and a controlled/limited driving operation can be continued (see Nakamori, Paragraph 50).
Regarding Claim 10, combination of Chen and Takizawa discloses the drive circuit according to Claim1, further comprising a second overcurrent detection circuit that detects an overcurrent in the switching element (Chen, comprising 220, Figure 1, Paragraph 34, “…When the drain voltage sense signal VDSEN reaches or exceeds Vref, the latch outputs a fault signal FLT of a predetermined level, e.g. 5V. The fault signal FLT is passed, via inverter 214 to the gate drive circuitry 210, e.g. as an input to AND gate 216, as shown in FIG. 1. The fault signal FLT is also passed directly to the fast soft turn-off circuitry 230”).
Chen does not disclose a first overcurrent detection circuit that detects an overcurrent in a motor, wherein the second OFF circuit is configured to extract charge from the gate of the switching element when the first overcurrent detection circuit detects the overcurrent in the motor and an extract charge from the gate of the switching element when the second overcurrent detection circuit detects the overcurrent in the switching element.
Nakamori discloses a control method for a drive circuit (Figures 1-5) comprising:
a switching element (comprising switching element/s in 1, Figures 1, 4-5);
an ON circuit that injects charge into a gate of the switching element according to a drive signal (ON circuit comprising 26 injects current a gate of switching element in 1 according to a drive signal CS, Figures 1, 4-5);
a first OFF circuit that extracts charge from the gate of the switching element in response to a drive signal (comprising 26 that extracts charge from the gate of the switching element in response to a drive signal CS, Figure 1); and
a second OFF circuit that is different from the first OFF circuit (comprising 61, Figure 1) and extracts charge from the gate of the switching element in response to an overcurrent detection signal (61 receives output of overcurrent/fault detection circuit comprising 22, 23, 24 and extracts charge from the gate of the switching element, Figures 1, 4-5),
a first overcurrent detection circuit that detects an overcurrent in a motor (comprising 22, 23 outputting SCU to 62, 70 63 and 28, Figures 1, 4-5, Column 3, lines 62-64, “…A three-phase load, such as a three-phase AC motor, is connected to the respective AC output terminals tu, tv, and tw”); and a second overcurrent detection circuit that detects an overcurrent in multiple phases/the switching elements (comprising 22, 23, 24 outputting Soc to 62, 69, Figures 1, 5),
wherein the second OFF circuit is configured to extract charge from the gate of the switching element when the first overcurrent detection circuit detects an overcurrent in a motor (output Scu of 23 directly and delayed, coupled to a gate of the second OFF circuit 61 via delay circuit 63 and OR 62, Figures 1, 4-5) and extract charge from the gate of the switching element when the second overcurrent detection circuit detects the overcurrent in the switching element (output Soc of 24 coupled to a gate of the second OFF circuit 61 via OR 62, Figures 1, 4-5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the drive circuit of Chen, an additional/second overcurrent detection circuit and the second OFF circuit being shared by the first and the second overcurrent detection circuit as taught by Nakamori, such that driving of switching elements can be halted instantaneously to protect the switching elements in all phases from destruction due to overcurrent (see Nakamori, Paragraph 57).
Claim 15 recites control method of Claim 11 with corresponding limitation of the drive circuit of Claim 10. Therefore, Claim 15 is rejected at least for the same reasons as for Claim 10.
Allowable Subject Matter
Claims 7-9, 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding amended Claim 7, combination of Chen and Takizawa discloses the drive circuit according to Claim 1, further comprising an AND circuit having an output connected to inputs of the ON circuit, the first OFF circuit, and an input connected to an overcurrent detection circuit (Chen, AND gate 216 with output connected to the input 212 comprising the ON circuit and first OFF circuit and the input connected to output of overcurrent detection circuit 220, Figure 1).
Combination of Chen and Takizawa does not an OR circuit having an output connected to inputs of the ON circuit, the first OFF circuit, and the second OFF circuit and an input connected to an overcurrent detection circuit.
Nakamori discloses a drive circuit (Figures 1-5) comprising:
a switching element (comprising a switching element in 1, Figures 1, 4-5);
an ON circuit that injects charge into a gate of the switching element according to a drive signal (ON circuit comprising 26, 21 injects current a gate of switching element in 1 according to a drive signal CS, Figures 1, 4-5), the ON circuit including a first transistor having a first source/drain terminal electrically coupled to the gate and a second source/drain terminal (comprising transistor 21 having source/drain terminal electrically coupled to the switching element in 1) ;
a first OFF circuit that extracts charge from the gate of the switching element in response to a drive signal (comprising 27, 21 that extracts charge from the gate of the switching element in response to a drive signal CS, Figure 1), the first OFF circuit including a second transistor having a third source/drain terminal electrically coupled to the gate and a fourth source/drain terminal coupled to a second resistor (comprising 27 having a third source/drain terminal electrically coupled to the gate of the switching element and a fourth source/drain terminal coupled to a second resistor 68); and
a second OFF circuit that is different from the first OFF circuit (comprising 61, Figure 1) and extracts charge from the gate of the switching element in response to an overcurrent detection signal (61 receives output of overcurrent/fault detection circuit comprising 22, 23, 24 and extracts charge from the gate of the switching element, Figures 1, 4-5),
an OR circuit (comprising 28, 62, 53, Figure 1) having an output connected to inputs of the ON circuit, and the second OFF circuit and an input connected to an overcurrent detection circuit (output of 28 connected to the input of 26, output of 62 connected to the input of 61 and an input of 53 connected to an overcurrent detection circuit coupled to 31, 32, 33, Toc, Figures 1, 4-5, Paragraph 49, “The individual overcurrent detection signal Scu, which has been inverted to the H-level, is supplied to the gate of the P-channel field effect transistor 26 via the OR circuit 28 to cause the P-channel field effect transistor 26 to be non-conductive”).
Chen, Takizawa, and Nakamori, alone in combination does not disclose the output of the OR circuit connected to input of the second OFF circuit, in combination with the other recited elements of Claim 7, and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8-9 depend from Claim 7 and are objected due to dependency to an objected claim.
Claims 13-14 recite control method of Claim 11 with corresponding limitation of the drive circuit of Claims 7, 9 respectively. Therefore, Claims 13-14 are objected for the same reason as for Claims 7, 9 respectively.
Response to Arguments
Applicant's arguments filed on 7/06/2026 have been fully considered but they are not persuasive and/or rendered moot in view of new grounds of rejection (102 rejection of Claims is changed to 103 rejection over Chen in view of newly found secondary reference Takizawa, for the teaching of the argued upon new limitations of independent Claims 1 and 11).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Igarashi et al. (US 2014/0092655) discloses a drive circuit (Figures 1-9) comprising: a switching element (comprising 103, Figure 1); a first overcurrent detection circuit that detects an overcurrent in a phase (comprising 107, Figure 1); and a second overcurrent detection circuit that detects an overcurrent in the switching elements (comprising 109, Figure 1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571)270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LUCY M THOMAS/Examiner, Art Unit 2838, 9/11/2026.
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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