Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
RESPONSE TO AMENDMENT
Acknowledgment is made of the amendment filed 03/23/2026, in which:claims 1 is amended; claim 17 is cancelled; and the rejections of the claims are traversed. Claims 1-16 and 18-21 are currently pending and an Office Action on the merits follows.
ALLOWABLE SUBJECT MATTER
Claims 4, 14-15, 18-19, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 is objected to because the cited references do not disclose “wherein the second conductive connection portion and the driving transistor are located on a same side of the first scanning signal line in the second direction; and in the first direction, an orthographic projection of the second conductive connection portion on the substrate is located on a side of the orthographic projection of the first conductive connection portion on the substrate away from an orthographic projection of the compensation transistor on the substrate.
Claim 14 is objected to because the cited references do not disclose “wherein an orthographic projection of the first electrode of the driving transistor on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line on the substrate”.
Claims 15 and 19 are objected to because the cited references do not disclose “wherein the compensation transistor a semiconductor structure, and the semiconductor structure includes a first portion, wherein an orthographic projection of the first portion on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and an orthographic projection of the driving transistor on the substrate; and the first portion is electrically connected to a first conductive connection and the orthographic projection of the first portion on the substrate overlaps with an orthographic projection of the second scanning signal line on the substrate; or the compensation transistor includes a semiconductor structure, the semiconductor structure includes a first portion, a second portion and a third portion; the second portion is a channel of the compensation transistor, the third portion is the first electrode of the compensation transistor; and the first portion is electrically connected to the first conductive connection portion wherein an orthographic projection of the first portion of on the substrate and an orthographic projection of the second scanning signal line on the substate have a first overlapping region and an area of the first overlapping region is greater than an area of an orthographic projection of the second portion on the substate. ”
Claim 18 is objected to because the cited references do not disclose “ wherein the semiconductor structure further includes a second portion and a third portion, the second portion is a channel of the compensation transistor, and the third portion is the first electrode of the compensation transistor; the pixel driving circuit further includes a third conductive connection portion, the first electrode of the compensation transistor is electrically connected to the third conductive connection portion, and the second electrode of the driving transistor is electrically connected to the third conductive connection portion; wherein an orthographic projection of the third conductive connection portion on the substrate overlaps with an orthographic projection of the second portion on the first substrate. “
Claim 21 is objected to because the cited references do not disclose wherein the semiconductor structure further includes a second portion and a third portion, the first sub-portion protrudes toward the data writing transistor relative to the second portion, and in the first direction, a width of the third portion is substantially equal to a width of the second portion.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-2, 5-12, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over WANG CN 115691419 in view of Lee et al US 20180114824.
Examiner’s note: For the purposes of claim mapping please refer to the Patent translation of CN 115691419 that has been provided.
Consider claim 1. Wang discloses an array substrate fig. 11 [0266] display substrate with array of sub-pixels, comprising:
a substrate [0261] display substrate comprising a substrate and a plurality of subpixels arranged on the substrate;
a plurality of pixel driving circuits fig. 3 fig. 6 fig. 8 fig. 36 all show pixel driving circuits located on a side of the substrate [0261] [0266] and arranged in a plurality of rows and a plurality of columns see fig. 11 where pixels P are arranged in rows and columns, wherein any pixel driving circuit of the plurality of pixel driving circuits includes:
a driving transistor fig. 3 fig. 6 fig. 8 fig. 36 T3, a compensation transistor electrically connected to the driving transistor fig. 3 fig. 6 fig. 8 fig. 36 T1, a first conductive connection portion fig. 3 fig. 6 fig. 8 fig. 36 conductive portion, e.g. wire, which connects control electrode of T3 with second electrode of T1, and a storage capacitor fig. 3 fig. 6 fig. 8 fig. 36 see capacitor C connected between T5 and T3; and
a plurality of first scanning signal lines located on the side of the substrate [0261], fig. 3 fig. 6 fig. 8 fig. 36 each pixel circuits has scan lines S1 S2 S3
wherein a control electrode of the driving transistor fig. 3 fig. 6 fig. 8 fig. 36 see gate of transistor T3 is electrically connected to the first conductive connection portion fig. 3 fig. 6 fig. 8 fig. 36 conductive portion, e.g. wire ,which connects control electrode of T3 with second electrode of T1, a control electrode of the compensation transistor fig. 3 fig. 6 fig. 8 fig. 36 see gate of transistor T1 is electrically connected to a first scanning signal line fig. 3 fig. 6 fig. 8 fig. 36 scan signal line S2, a second electrode of the compensation transistor is electrically connected to the first conductive connection portion fig. 3 fig. 6 fig. 8 fig. 36 conductive portion, e.g. wire ,which connects second electrode of T1 with second electrode of T3 via node n1 , and a first electrode of the compensation transistor is electrically connected to a second electrode of the driving transistor fig. 3 fig. 6 fig. 8 fig. 36 first electrode of T1 connects with second electrode of T3 via node n3; and a first plate of the storage capacitor is electrically connected to the control electrode of the driving transistor fig. 3 fig. 6 fig. 8 fig. 36 see capacitor C first plate is electrically connected to T3 ;
an orthographic projection of the first scanning signal line on the substrate is non- overlapping with an orthographic projection of the first conductive connection portion on the substrate. see fig. 14 below. 73 does not overlap the first scanning signal line S2. also see fig. 22 which illustrates connection portion 73.
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an orthographic projection of the second electrode of the compensation transistor on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and an orthographic projection of the first plate of h storge capacitor on the substrate fig. 3 fig. 6 fig. 8 fig. 36 the electrodes of T1 are between first scanning signal line S2 and the first plate of capacitor C.
Wang does not explicitly disclose the scanning lines extending in a first direction and arranged in a second direction, wherein the second direction intersects the first direction;
Lee however discloses extending in a first direction and arranged in a second direction, wherein the second direction intersects the first direction see fig. 2 see scan lines S1-Sn extending from left to right and arranged top to bottom.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display of Wang to include extending in a first direction and arranged in a second direction, wherein the second direction intersects the first direction, as taught by Lee, to enable sequential selection of pixels in the horizontal line unit [0058] and also to provide a high-resolution display device that provides a high-quality image without defects, such as bright spots or random display irregularities [0006].
Consider claim 2. Wang as modified by Lee disclose the array substrate according to claim 1, wherein the any pixel driving circuit further includes a second conductive connection portion see Wang fig. 22 71, and a first electrode of the driving transistor See Wang fig. 3 fig. 6 fig. 8 fig. 36 first electrode of T3 is electrically connected to the second conductive connection portion Wang fig. 14 fig. 22 71 is connected to first electrode of T3;
wherein the orthographic projection of the first scanning signal line on the substrate is non-overlapping with an orthographic projection of the second conductive connection portion on the substrate See Wang fig. 14 fig. 22 71 does not overlap the first scanning signal line S2.
Consider claim 5. Wang as modified by Lee disclose the array substrate according to claim 1 wherein the orthographic projection of the first scanning signal line on the substrate is non-overlapping with an orthographic projection of the control electrode of the driving transistor on the substrate Wang fig. 14 and fig. 16 S2 does not overlap with control electrode of driving transistor T3-g.
Consider claim 6. Wang as modified by Lee disclose the array substrate according to claim 1 wherein the orthographic projection of the first scanning signal line on the substrate is non-overlapping with an orthographic projection of a first electrode of the driving transistor on the substrate Wang fig. 14 and fig. 26 S2 does not overlap with first electrode of driving transistor T3; and/or the orthographic projection of the first scanning signal line on the substrate is non- overlapping with an orthographic projection of the second electrode of the driving transistor on the substrate Wang fig. 14 and fig. 26 S2 does not overlap with second electrode of driving transistor T3.
Consider claim 7. Wang as modified by Lee disclose the array substrate according to any-e-, further comprising:
a plurality of data writing signal lines located on the side of the substrate fig. 3 fig. 6 fig. 8 fig. 36 all show pixel driving circuits with data line D1. Lee fig. 2 data lines D1-D2, and extending in the second direction and arranged in the first direction Lee fig. 2 data lines D1-D2 extending in y-direction and arranged in a x-direction; and
a plurality of second scanning signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction see Lee fig. 2 see scan lines S1-Sn extending from x direction and arranged y direction. Wang fig. 3 fig. 6 fig. 8 fig. 36 S1;
wherein the pixel driving circuit further includes a data writing transistor Wang fig. 3 fig. 6 fig. 8 fig. 36 data writing transistor T4, a first electrode of the data writing transistor is electrically connected to a data writing signal line Wang fig. 3 fig. 6 fig. 8 fig. 36 source of T4 is connected to D1, a second electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor Wang fig. 3 fig. 6 fig. 8 fig. 36 drain of T4 is connected to source of T3, and a control electrode of the data writing transistor is electrically connected to a second scanning signal line Wang fig. 3 fig. 6 fig. 8 fig. 36 gate of T4 is connected to S1; and in the first direction, an orthographic projection of the data writing transistor on the substrate is located on a side of an orthographic projection of the driving transistor on the substrate away from an orthographic projection of the compensation transistor on the substrate Wang fig. 14 and fig. 26 T4 and T3 are on a side which is away from compensation transistor T1.
Motivation to combine is similar to motivation in claim 1.
Consider claim 8. Wang as modified by Lee disclose the array substrate according to claim 7, wherein in the second direction, the orthographic projection of the first scanning signal line on the substrate is located on a side of an orthographic projection of the second scanning signal line on the substrate away from the orthographic projection of the driving transistor on the substrate Wang fig. 14 and fig. 26 S2 is located below S1 on a second direction and is away from drive transistor T3.
Consider claim 9. Wang as modified by Lee disclose the array substrate according to claim 7, wherein the orthographic projection of the first scanning signal line on the substrate is non-overlapping with an orthographic projection of the second electrode of the data writing transistor on the substrate. Wang fig. 26 S2 does not overlap with the second electrode of data writing transistor T4.
Consider claim 10. Wang as modified by Lee disclose the array substrate according to further comprising:
a plurality of first initialization signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction Wang fig. 2 fig. 3 Vint1 Vinit2 DR. Lee fig. 2 Initialization power line Vint; and
a plurality of first reset signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction Wang fig. 2 R1 S3 are the Reset lines.
wherein the pixel driving circuit further includes a first reset transistor Wang See Wang fig. 3 fig. 6 fig. 8 fig. 36 first reset transistor T2.
a control electrode of the first reset transistor is electrically connected to a first reset signal line See Wang fig. 3 fig. 6 fig. 8 fig. 36 first reset transistor T2 connected to R1, a first electrode of the first reset transistor is electrically connected to a first initialization signal line See Wang fig. 3 fig. 6 fig. 8 fig. 36 first electrode of first reset transistor T2 connected to Vinit1, and a second electrode of the first reset transistor is electrically connected to the second electrode of the driving transistor See Wang fig. 3 fig. 6 fig. 8 fig. 36 second electrode of first reset transistor T2 connected to drain electrode of T3; and
in the second direction, an orthographic projection of the first reset signal line on the substrate is located on a side of the orthographic projection of the first scanning signal line on the substrate away from an orthographic projection of the driving transistor on the substrate Wang fig. 14 and fig. 26 R1 is on a side of S2 and is away from driving transistor T3.
Motivation to combine is similar to motivation in claim 1.
Consider claim 11. Wang as modified by Lee disclose the array substrate according to further comprising:
a plurality of enable signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction Wang fig. 3 E1. Lee fig. 2 E1-En and;
a plurality of first power supply signal lines located on the side of the substrate, extending in the second direction and arranged in the first direction Wang fig. 3 VDD. Lee fig. 2 ELVDD.
wherein the pixel driving circuit further includes a first light-emitting control transistor See Wang fig. 3 fig. 6 fig. 8 fig. 36 light emitting control transistor T5, wherein a control electrode of the first light-emitting control transistor is electrically connected to an enable signal line Wang fig. 3 fig. 6 fig. 8 fig. 36 control electrode of light emitting control transistor T5 is connected to E1, a first electrode of the first light-emitting control transistor is electrically connected to a first power supply signal line Wang fig. 3 fig. 6 fig. 8 fig. 36 source electrode of light emitting control transistor T5 is connected to VDD, and a second electrode of the first light- emitting control transistor is electrically connected to a first electrode of the driving transistor Wang fig. 3 fig. 6 fig. 8 fig. 36 source electrode of light emitting control transistor T5 is connected to VDD,
in the second direction an orthographic projection of the enable signal line on the substrate is located on a side of an orthographic projection of the driving transistor on the substrate away from the orthographic projection of the first scanning signal line on the substrate Wang fig. 14 and fig. 26 E1 is on a side driving transistor T3 and is away from S2.
Motivation to combine is similar to motivation in claim 1.
Consider claim 12. Wang as modified by Lee disclose the array substrate according to claim 11, further comprising:
a plurality of second initialization signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction See Wang fig. 3 fig. 6 fig. 8 fig. 36 Vinit2; and
a plurality of second reset signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction See Wang fig. 3 fig. 6 fig. 8 fig. 36 S3 which acts as a reset signal;
wherein the pixel driving circuit further includes a second reset transistor See Wang fig. 3 fig. 6 fig. 8 fig. 36 S3 second reset transistor T7;
a control electrode of the second reset transistor is electrically connected to a second reset signal line See Wang fig. 3 fig. 6 fig. 8 fig. 36 S3 control electrode of second reset transistor T7 is connected to reset signal S3, a first electrode of the second reset transistor is electrically connected to a second initialization signal line See Wang fig. 3 fig. 6 fig. 8 fig. 36 S3 first electrode of second reset transistor T7 is connected to Vinit2, and a second electrode of the second reset transistor is electrically connected to a light-emitting device See Wang fig. 3 fig. 6 fig. 8 fig. 36 S3 second electrode of second reset transistor T7 is connected to LED O1; and
in the second direction, an orthographic projection of the second reset signal line on the substrate is located on a side of the orthographic projection of the enable signal line on the substrate away from the orthographic projection of the driving transistor on the substrate Wang fig. 14 and fig. 26 S3 is on a side E1 and is away from driving transistor T3.
Consider claim 16. Wang as modified by Lee disclose the array substrate according to claim 7, wherein the compensation transistor a semiconductor structure;
the semiconductor structure includes a first portion, and an orthographic projection of the first portion on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and an orthographic projection of the driving transistor on the substrate Wang fig. 26 fig. 32 compensation transistor T1 has a first portion between first scanning signal line S2 and driving transistor T3. ; and
in an extension direction of the second scanning signal line, the first portion includes a first sub-portion and a second sub-portion that connected Wang fig. 26 fig. 32 compensation transistor T1 has a first portion which can be subdivided into a first portion and a second portion. The first portion being the area that overlaps S2; wherein an orthographic projection of the second sub-portion on the substrate is located between an orthographic projection of the first sub-portion on the substrate and an orthographic projection of the control electrode of the compensation transistor on the substrate, and the first sub-portion is electrically connected to the first conductive connection portion Wang fig. 26 fig. 32 compensation transistor T1 has a second sub portion between first sub portion and control electrode which is connected to the first conductive connection portion 73 see fig. 22.
;wherein orthographic projections of the first sub-portion and the second sub-portion on the substrate both overlap with an orthographic projection of the second scanning signal line on the substrate Wang fig. 26 fig. 32 the first and second sub portion both overlap S2.
Consider claim 20. Wang as modified by Lee disclose a display panel Wang [0006] display device, comprising:
the array substrate according to claim 1;and
a light-emitting device layer located on a side of the array substrate, wherein the light-emitting device layer includes a plurality of light-emitting devices, a light-emitting device is electrically connected to a pixel driving circuit in the array substrate See Wang fig. 3 fig. 6 fig. 8 fig. 36 S3 the pixel circuit connected to LED O1 [0123]. Also see Lee [0090-0091] fig. 4 118 light emitting element;
2. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over WANG CN 115691419 (English translation of the specification is provided herewith) in view of Lee et al US 201801444824 and further in view of Wang et al. US 20230180552 hereinafter “Wang2”.
Consider claim 3. Wang as modified by Lee disclose the array substrate according to claim 1, but do not disclose wherein the orthographic projection of the first conductive connection portion on the substrate is located between an orthographic projection of the driving transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate
Wang2 however discloses wherein the orthographic projection of the first conductive connection portion on the substrate is located between an orthographic projection of the driving transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate see fig. 5 where the connecting portion between via 9 and via 7 (first conductive connection portion) is between T3 and first scanning signal line 114A.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display of Wang as modified by Lee to include wherein the orthographic projection of the first conductive connection portion on the substrate is located between an orthographic projection of the driving transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate, as taught by Wang2, to enable improved circuit layout while increasing screen resolution while meeting performance requirements [0041][0044].
3. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over WANG CN 115691419 (English translation of the specification is provided herewith) in view of Lee et al US 201801444824 and further in view of Wang et al. US 20240379686 hereinafter “Wang3”.
Consider claim 13. Wang as modified by Lee disclose the array substrate according to claim 12, further comprising:
a plurality of third initialization signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction See Wang fig. 3 fig. 6 fig. 8 fig. 36 DR; and
a plurality of third reset signal lines located on the side of the substrate, and extending in the first direction and arranged in the second direction See Wang fig. 3 fig. 6 fig. 8 fig. 36 S3;
wherein the pixel driving circuit further includes a third reset transistor See Wang fig. 3 fig. 6 fig. 8 fig. 36 third reset transistor T8 ;
a control electrode of the third reset transistor is electrically connected to a third reset signal line See Wang fig. 3 fig. 6 fig. 8 fig. 36 control electrode of the third reset transistor T8 is connected to reset signal S3, a first electrode of the third reset transistor is electrically connected to a third initialization signal line See Wang fig. 3 fig. 6 fig. 8 fig. 36 a first electrode of the third reset transistor T8 is connected to third initialization signal line DR, and a second electrode of the third reset transistor is electrically connected to a first electrode of the driving transistor See Wang fig. 3 fig. 6 fig. 8 fig. 36 a second electrode of the third reset transistor T8 is connected to driving transistor T3; and
Wang as modified by Lee do not disclose the orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of the third initialization signal line on the substrate Wang fig. 14 and fig. 26 E1 partially overlaps DR.
Wang3 however discloses the orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of the third initialization signal line on the substrate [0048] since the wirings of the space are dense the emission control signal line EM and initialization signal line at different layers are partially overlapped.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display of Wang as modified by Lee to include the known technique of the orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of the third initialization signal, as taught by Wang3, to accommodate dense wire spacings [0048].
RESPONSE TO ARGUMENTS
Applicant's arguments have been fully considered but are moot in view of the new grounds of rejection.
The Applicant argues (pages 11-12) that in the invention T3 is directly electrically connected to M1 and T2 is directly electrically connected to M1. In contrast, Wang discloses T1 is coupled to 73 and 73 is directly coupled to T9 and T9 is directly coupled to T3.
The Office however respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., direct connections between the transistors and conductive connection portions) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The Applicant argues ( page 13) that Wang and Lee do not disclose the orthographic projection relationship on the substrate between the second scan line S2 and the first node N1 .
The Office respectfully disagrees. Wang clearly illustrates in fig. 14 (see above) 73 does not overlap the first scanning signal line S2. Also see fig. 22 which illustrates connection portion 73.
The Applicant argues (pages 14-15) that Wang and Lee do not disclose the features of the amended claim i.e. an orthographic projection of the second electrode of the compensation transistor on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and an orthographic projection of the first plate of h storge capacitor on the substrate.
The Office respectfully disagrees. Wang clearly illustrates in fig. 3 fig. 6 fig. 8 fig. 36 the electrodes of T1 are between first scanning signal line S2 and the first plate of capacitor C. In addition, the Applicant provides paragraphs [0098], [0110], [0187][0273][0307] and figs. 5, 9, 11, 13-14 and 16 as support for the amended language. However, only fig. 5 shows that b2 (second electrode of T2 compensation transistor) between S1 (first plate of storage capacitor) and G1 (first scanning signal line). The other figures and paragraphs only recite that the G1 is non-overlapping with b2 of T2. None of the figures 9, 11, 13-14 and 16 show b2 being between G1 and S1. Rather fig. 16 shows b2 being below G1 and c3 (c3/S1/Cst fig. 11).
V. CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2628
/IBRAHIM A KHAN/ 04/15/2026Primary Examiner, Art Unit 2628
Prosecution Insights