DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in JAPAN on 03/31/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/26/2024 is being considered by the examiner.
Claim Objections
Claim 6 is objected to because of the following informalities: ‘the extending direction” should be “an extending direction”. Appropriate correction/explanation is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the mounting region" in the second or third line of the claim. There is insufficient antecedent basis or location relation to other elements presented in the claim for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, and 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by UENO (JP2011187683).
Regarding Claim 1. UENO teaches, in Fig. 4-7, a wiring board comprising:
an insulating layer (171-173) comprising a first surface and a second surface opposite to the first surface (see Fig. 4-7);
a conductive layer (130,140,150) located on the first surface (semiconductor mounting surface) and comprising a plurality of signal conductors (130, 132, 133), a ground conductor (140, 131g), and a power supply conductor (150, 131v);
a plurality of via hole conductors (182) penetrating through the insulating layer and located from the first surface to the second surface (see Fig. 4-7); and
a via hole conductor connecting portion located on the first surface (see Fig. 5-7) and configured to connect a part of the plurality of via hole conductors to the ground conductor and/or the power supply conductor (182v, 182g/161g), wherein
the plurality of signal conductors are conductors having a long shape (see Fig. 4-7) and comprising a first end and a second end (see Fig. 4-7),
the first surface of the insulating layer comprises:
a first region (region between 131s and rightmost 182g) in which the via hole conductor connecting portion is located;
a second region (131s area) in which the first end of the plurality of signal conductors located in the first region is located; and
a third region (rightmost 182g area) in which the second end of the plurality of signal conductors located in the first region is located,
in a plan view,
the first region is located between the second region and the third region (see Fig. 6),
in the first region, the via hole conductor connecting portion (182v, 182g/161g) is disposed in a lattice pattern in a first direction (direction where 131s are arranged) along a longitudinal direction in which the first end of the plurality of signal conductors in the second region is arranged, and in a second direction (direction perpendicular to first direction) intersecting the first direction (see Fig. 6),
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a portion of the via hole conductor connecting portion (excluding the bottom left 182v and 182g in Fig. 6) comprises:
a first connecting portion (top left 182v);
a second connecting portion (top middle left 182v) adjacent to the first connecting portion in the first direction;
a third connecting portion (middle bottom left 182v) adjacent to the second connecting portion in the first direction;
a fourth connecting portion (top left 182g/161g) adjacent to the first connecting portion in the second direction;
a fifth connecting portion (top middle left 182g/161g) adjacent to the fourth connecting portion in the first direction; and
a sixth connecting portion (middle bottom left 182g/161g) adjacent to the fifth connecting portion in the first direction,
a part of the signal conductors comprises:
a first wiring group (see drawings above) comprising a plurality of wiring lines extending in a region between the first connecting portion and the second connecting portion (see Fig. 6); and
a second wiring group (see drawings above) comprising a plurality of wiring lines extending in a region between the second connecting portion and the third connecting portion (see Fig. 6),
the first wiring group (see drawings above) comprises:
a first portion (see drawings above) extending from a region between the second connecting portion and the fifth connecting portion to a region between the fifth connecting portion and the sixth connecting portion (see Fig. 6); and
a second portion (see drawings above) extending in a region between the fourth connecting portion and the fifth connecting portion (see Fig. 6), and
the second wiring group comprises:
a third portion (see drawings above) extending in a region between the fifth connecting portion and the sixth connecting portion (see Fig. 6); and
a fourth portion (see drawings above) extending in a region between the third connecting portion and the sixth connecting portion (see Fig. 6).
Regarding Claim 2. UENO teaches the wiring board according to claim 1, wherein
the first direction and the second direction are orthogonal to each other (see Claim 1).
Regarding Claim 4. UENO teaches the wiring board according to claim 1, wherein
in the plurality of signal conductors, a pitch between the signal conductors at the first end (131s side) is smaller than a pitch between the signal conductors at the second end (182s side) (see Fig. 6).
Regarding Claim 5. UENO teaches the wiring board according to claim 1, wherein
the first surface of the insulating layer comprises a quadrangular fourth region (111 region) overlapping the mounting region in a perspective plan view (see Fig. 5), and the second region comprises a corner portion located at a corner of the fourth region and/or a side portion located along a side of the fourth region (see Fig. 5).
Regarding Claim 7. UENO teaches A mounting structure comprising:
the wiring board according to claim 1; and
an electronic component (111) located in a mounting region of the wiring board (see Fig. 4).
Regarding Claim 8. Ueno teaches the mounting structure according to claim 7, wherein
an outer edge of the mounting region (111 area) is located along the first direction in a plane perspective (see Fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over UENO in view of YONEHARA (WO2010/073832).
Regarding Claim 3. UENO teaches the wiring board according to claim 1, but does not teach wherein the plurality of signal conductors comprise a plurality of paired wiring lines, and the via hole conductor connecting portion is not interposed between wiring lines constituting the paired wiring lines.
YONEHARA teaches, in Fig. 2. the plurality of signal conductors comprise a plurality of paired wiring lines (#1,#2,#3) ([0024]), and the via hole conductor connecting portion is not interposed between wiring lines constituting the paired wiring lines (rearrangement of parts in order to not affect its electrical transmission).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the wire board as disclosed by UENO with the paired wiring lines as disclosed by YONEHARA in order to reduce the deterioration of signal without reducing density of signal lines (YONEHARA, abstract).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over UENO in view of OSONO (JP2019079988).
Regarding Claim 6. UENO teaches the wiring board according to claim 5, but does not teach the plurality of signal conductors comprise a first signal conductor comprising the first end located at the corner portion and a second signal conductor comprising the first end located at the side portion, and a number of turning points at which an extending direction of the first signal conductor is changed is smaller than a number of turning points at which the extending direction of the second signal conductor is changed.
OSONO teaches, in Fig. 2, the plurality of signal conductors comprise a first signal conductor comprising the first end located at the corner portion (see 2s at the corner) and a second signal conductor comprising the first end located at the side portion (see 2s at the side), and a number of turning points at which an extending direction of the first signal conductor is changed is smaller than a number of turning points at which the extending direction of the second signal conductor is changed (as the structure of Fig. 2 shows that the signal conductors are moving in a corner direction such that the side conductor would need more turns than the corner portion in order to move in that direction and to avoid close contact with other signal conductors as it is known in the art)(rearrangement of parts- see In re Japikse, 86 USPQ 70 (CCPA 1950)).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the wring board as disclosed by UENO with the placement and orientation of the signal conductors as disclosed by OSONO in order to prevent impedance mismatch between signal conductors and reduced electrical characteristics (OSONO, [0004]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is presented in the Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMED AZAM whose telephone number is (571)270-0593. The examiner can normally be reached Mon-Fri 11:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY DOLE can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MA/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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