DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to application filed on September 26, 2024.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 9/26/2024 has been considered by the examiner.
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
5. Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Sekimoto (US 2012/0127768) in view of Fujita et al (US 2014/0346877).
Regarding claim 1, Sekimoto discloses an inverter circuit (i.e. circuit of Figure 2) capable of converting DC input voltage (Fig. 2, voltage Vdc) of a DC power supply (Fig. 2, DC power supply providing voltage Vdc) into AC output voltage (Fig. 2, AC voltage outputted from switching section 4a) of a predetermined frequency, the inverter circuit (i.e. circuit of Figure 2) comprising:
a series circuit (Fig. 2, circuit of switching elements Sp and Sn) in which a control switch (Fig. 2, switching element Sp) and a synchronous rectification switch (Fig. 2, switching element Sn) are connected in series, the series circuit (Fig. 2, circuit of switching elements Sp and Sn) being connected in parallel to the DC power supply (Fig. 2, DC power supply providing voltage Vdc); and
a control circuit (Fig. 1, switching control section 11 and inverter control section 15) (note that Figure 1 is related to Figure 2 since Figure 1 shows the controller of the inverter shown in Figure 2) that performs control of turning off the control switch (Fig. 2, switching element Sp) and turning on the synchronous rectification switch (Fig. 2, switching element Sn) after turning on the control switch (Fig. 2, switching element Sp) for first ON time (Fig. 3, time Tp) (See ¶[0034]) (note that Figure 3 is related to Figure 2 since Figure 3 shows the timing diagram of the controller for the inverter in Figure 2), and turning off the synchronous rectification switch (Fig. 2, switching element Sn) and turning on the control switch (Fig. 2, switching element Sp) after turning on the synchronous rectification switch (Fig. 2, switching element Sn) for second ON time (Fig. 3, time when gate signal Gn is high and gate signal Gp is low) so as to generate reverse current in an entire range of an instantaneous value of the AC output voltage (Fig. 2, AC voltage outputted from switching section 4a) (See Abstract and ¶[0034]-[0036]).
Sekimoto fails to explicitly disclose a reactor having one end connected to a connection point between the control switch and the synchronous rectification switch; and an output capacitor that is connected between a power supply line of the DC power supply and another end of the reactor and outputs the AC output voltage to both ends and to generate a reverse current in the reactor.
However, Fujita et al discloses a reactor (Fig. 1, inductor Lf1) having one end (Fig. 1, end of inductor Lf1 connected to shared node between switches Q1 and Q2) connected to a connection point (Fig. 1, shared node between switches Q1 and Q2) between a control switch (Fig. 1, switch Q1) and a synchronous rectification switch (Fig. 1, switch Q2); an output capacitor (Fig. 1, capacitor Cf1) that is connected between a power supply line (Fig. 1, supply line between power sources psp and psn) of a DC power supply (Fig. 1, power source 30) and another end (Fig. 1, end of inductor Lf1 connected to capacitor Cf1) of the reactor (Fig. 1, inductor Lf1) and outputs the AC output voltage (Fig. 1, voltage outputted from filter circuit 5) to both ends and to generate a reverse current in the reactor (Fig. 1, inductor Lf1).
Therefore, it would have been obvious, to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Sekimoto, by including a reactor and output capacitor, as taught by Fujita et al, in order to obtain a circuit capable of filtering transients or high-frequency components from an AC voltage outputted to a load.
Allowable Subject Matter
8. Claim 8-14 are allowed.
9. Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2 and 7, the prior art fails to disclose or suggest the emboldened and italicized features below:
An inverter circuit,
wherein a current value of the reverse current is obtained based on an inductance value of the reactor, a capacitance value of a capacitor connected in parallel to the control switch, a detection value of the DC input voltage, and a detection value of an instantaneous value of the AC output voltage.
Regarding claim 3, the prior art fails to disclose or suggest the emboldened and italicized features below:
An inverter circuit,
wherein a current value of the reverse current is a fixed value obtained based on an inductance value of the reactor, a capacitance value of a capacitor connected in parallel to the control switch, and a detection value of the DC input voltage.
Regarding claim 4, the prior art fails to disclose or suggest the emboldened and italicized features below:
An inverter circuit,
wherein a current value of the reverse current is a value obtained by adding a harmonic component of a frequency of the AC output voltage to a fixed value obtained based on an inductance value of the reactor, a capacitance value of a capacitor connected in parallel to the control switch, and a detection value of the DC input voltage.
Regarding claim 5, the prior art fails to disclose or suggest the emboldened and italicized features below:
An inverter circuit,
wherein the control circuit controls the first ON time and the second ON time so that the reverse current has a predetermined current value based on a detection value of the DC input voltage, a detection value of an instantaneous value of the AC output voltage, and a detection value of the AC output current.
Regarding claim 6, the prior art fails to disclose or suggest the emboldened and italicized features below:
An inverter circuit,
wherein the control circuit performs control to provide dead time in which both the control switch and the synchronous rectification switch are turned off while the control switch is turned on after the synchronous rectification switch is turned off.
Regarding claims 8-14, the prior art fails to disclose or suggest the emboldened and italicized features below:
An inverter circuit capable of converting DC input voltage of a DC power supply into AC output voltage of a predetermined frequency, the inverter circuit comprising:
a first series circuit in which a first switch and a second switch are connected in series, the first series circuit being connected in parallel to the DC power supply;
a second series circuit in which a third switch and a fourth switch are connected in series, the second series circuit being connected in parallel to the DC power supply;
a reactor having one end connected to a connection point between the first switch and the second switch;
an output capacitor that is connected between a connection point between the third switch and the fourth switch and another end of the reactor and outputs the AC output voltage to both ends; and
a control circuit that performs control of turning on the third switch and turning off the fourth switch and, after turning on the first switch as a control switch for first ON time, turning off the first switch and turning on the second switch as a synchronous rectification switch, and, after turning on the second switch for second ON time, turning off the second switch and turning on the first switch in a half cycle in which the AC output voltage is positive, and performs control of turning off the third switch and turning on the fourth switch and, after turning on the second switch as a control switch for first ON time, turning off the second switch and turning on the first switch as a synchronous rectification switch, and, after turning on the first switch for second ON time, turning off the first switch and turning on the second switch in a half cycle in which the AC output voltage is negative so as to generate reverse current in the reactor in an entire range of an instantaneous value of the AC output voltage.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamakoshi (US 2020/0252062) deals with a bridge output circuit, power device and semiconductor device, Shiina et al (US 9,479,054) deals with a buck converter with reverse current detection and pseudo ripple generation, Knowles et al (US 2014/0247633) deals with an intrinsic adaptive and autonomic piezotransformer circuits, Huang et al (US 2014/0185330) deals with a DC to DC power converting device, Gu et al (US 2014/0160799) deals with a DC/DC converter with resonant converter stage and buck stage and method of controlling the same, Thieringer et al (US 2012/0228938) deals with a DC-AC inverter assembly, in particular solar cell inverter, Williams et al (US 7,746,042) deals with a low-noise DC/DC converter with controlled conduction, and Mehta (US 2008/0080220) deals with an inverter with improved overcurrent protection circuit, and power supply and electronic ballast therefor.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY NASH whose telephone number is (571) 270-3349. The examiner can normally be reached on Monday-Friday 8am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner‘s supervisor, Thienvu Tran can be reached on (571) 270-1276. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY A NASH/Primary Examiner, Art Unit 2838
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