DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other Refs: Zhao (US 11194473) Programming frequently read data to low latency portions of a SSD.
Allowable Subject Matter
Claims 4, 5, 15, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
For Claims 4, the prior art discloses and/or renders obvious the limitations from Claims 1, 2, 11 and 3. The prior art does not appear to disclose the limitations from Claims 4.
For Claims 5, the prior art discloses and/or renders obvious the limitations from Claims 1, 2, 11 and 3. The prior art does not appear to disclose the limitations from Claims 5.
For Claims 15, the prior art discloses and/or renders obvious the limitations from Claim 9, 12, 13, and 14. The prior art does not appear to disclose the limitations from Claims 15.
For Claims 16, the prior art discloses and/or renders obvious the limitations from Claim 9, 12, 13, and 14. The prior art does not appear to disclose the limitations from Claims 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20090193184) and in view of Cariello (US 20200210067) and further in view of Pratt (US 20220050627)
Claim 1. Yu discloses
A data writing method for a storage device (eg., 0017-0018 Fig. 16 - flash systems… data writes; 0040 Fig 1 - hybrid flash memory ), comprising:
obtaining a first storage mode of the storage device (eg., [0052] In FIG. 2C, A MLC flash device is being operated in a SLC mode );
writing first data into the storage device in a second storage mode corresponding to the first storage mode of the storage device, wherein the first data is configured for changing the first storage mode of the storage device to a third storage mode, and the third storage mode is supported in the storage device (eg., 0052, 0055 In FIG. 2C, A MLC flash device is being operated in a SLC mode to emulate a SLC flash.);
writing data into the storage device in the third storage mode in response to the first data being executed (eg., 0052 - A MLC flash device is being operated in a SLC mode to emulate a SLC flash. Some MLC flash chips may provide a SLC mode).
Yu does not disclose, but Careillo discloses
wherein the first data is configured for changing the storage mode of the storage device to a third storage mode (eg., 0023 - a pseudo SLC (pSLC) is described that can be used within an MLC block. The enables a switch from slow MLC writes (e.g., two-level MLC, TLC, QLC, etc.) to fast single level writes—pSLC).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello providing the benefit of a mixed encoding (see Cariello, 0023) to address the current need in the art to quickly store the write data from the host—because SLC writes are often much faster than MLC writes. This enables the host to move on to other tasks while the memory device takes the time it needs to transcribe that data to TLC blocks (e.g., in the background) for final storage (see Cariello, 0020).
Yu in view of Careillo does not disclose, but Pratt discloses
wherein the first data is program data related to storage modes of the storage device and is capable of being read and executed by a host controller of the storage device to enable the host controller to support a storage mode corresponding to the first data, for changing the first storage mode of the storage device to a third storage mode (eg., 0026 - a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells that are dynamic SLCs, meaning the memory cells can be used in either of an SLC mode or a non-SLC mode (e.g., MLCs, TLCs, QLCs) and can be converted from one to the other ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello, with Pratt, providing the benefit of it can be beneficial to store data in an SLC mode to withstand higher temperatures and then return to using cells storing data in a non-SLC mode when temperatures fluctuate less or are more likely to be at a lower temperature (see Pratt, 0027) storage mode component resident on the memory sub-system (e.g., on the memory sub-system controller), to make it possible to control the storage mode of the memory sub-system (0014).
Claim 9. Yu discloses
A storage device, comprising a memory and a processor, wherein the memory is configured to store data, and the data is capable of being executed by the processor (eg., [0056] FIG. 3A shows a host system using flash modules. Motherboard system controller 404 connects to Central Processing Unit (CPU) 402 over a front-side bus or other high-speed CPU bus. CPU 402 reads and writes SDRAM buffer 410, which is controlled by volatile memory controller 408. SDRAM buffer 410 may have several memory modules of DRAM chips.).
obtaining a first storage mode of the storage device (eg., [0052] In FIG. 2C, A MLC flash device is being operated in a SLC mode );
writing first data into the storage device in a second storage mode corresponding to the first storage mode of the storage device, wherein the first data is configured for changing the first storage mode of the storage device to a third storage mode, (eg., 0052, 0055 In FIG. 2C, A MLC flash device is being operated in a SLC mode to emulate a SLC flash.);
writing data into the storage device in the third storage mode in response to the first data being executed (eg., 0052 - A MLC flash device is being operated in a SLC mode to emulate a SLC flash. Some MLC flash chips may provide a SLC mode).
Yu does not disclose, but Careillo discloses
wherein the first data is configured for changing the storage mode of the storage device to a third storage mode (eg., 0023 - a pseudo SLC (pSLC) is described that can be used within an MLC block. The enables a switch from slow MLC writes (e.g., two-level MLC, TLC, QLC, etc.) to fast single level writes—pSLC).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello providing the benefit of a mixed encoding (see Cariello, 0023) to address the current need in the art to quickly store the write data from the host—because SLC writes are often much faster than MLC writes. This enables the host to move on to other tasks while the memory device takes the time.
Yu in view of Careillo does not disclose, but Pratt discloses
wherein the first data is program data related to storage modes of the storage device and is capable of being read and executed by a host controller of the storage device to enable the host controller to support a storage mode corresponding to the first data, for changing the first storage mode of the storage device to a third storage mode (eg., 0026 - a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells that are dynamic SLCs, meaning the memory cells can be used in either of an SLC mode or a non-SLC mode (e.g., MLCs, TLCs, QLCs) and can be converted from one to the other ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello, with Pratt, providing the benefit of it can be beneficial to store data in an SLC mode to withstand higher temperatures and then return to using cells storing data in a non-SLC mode when temperatures fluctuate less or are more likely to be at a lower temperature (see Pratt, 0027) storage mode component resident on the memory sub-system (e.g., on the memory sub-system controller), to make it possible to control the storage mode of the memory sub-system (0014).
Claim 10. Yu discloses
A computer-readable storage medium, storing program data that is capable of being executed by a processor (eg., [0056] FIG. 3A shows a host system using flash modules. Motherboard system controller 404 connects to Central Processing Unit (CPU) 402 over a front-side bus or other high-speed CPU bus. CPU 402 reads and writes SDRAM buffer 410, which is controlled by volatile memory controller 408. SDRAM buffer 410 may have several memory modules of DRAM chips.).
obtaining a first storage mode of the storage device (eg., [0052] In FIG. 2C, A MLC flash device is being operated in a SLC mode );
writing first data into the storage device in a second storage mode corresponding to the first storage mode of the storage device, wherein the first data is configured for changing the first storage mode of the storage device to a third storage mode, (eg., 0052, 0055 In FIG. 2C, A MLC flash device is being operated in a SLC mode to emulate a SLC flash.);
writing data into the storage device in the third storage mode in response to the first data being executed (eg., 0052 - A MLC flash device is being operated in a SLC mode to emulate a SLC flash. Some MLC flash chips may provide a SLC mode).
Yu does not disclose, but Careillo discloses
wherein the first data is configured for changing the storage mode of the storage device to a third storage mode (eg., 0023 - a pseudo SLC (pSLC) is described that can be used within an MLC block. The enables a switch from slow MLC writes (e.g., two-level MLC, TLC, QLC, etc.) to fast single level writes—pSLC).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello providing the benefit of a mixed encoding (see Cariello, 0023) to address the current need in the art to quickly store the write data from the host—because SLC writes are often much faster than MLC writes. This enables the host to move on to other tasks while the memory device takes the time.
Yu in view of Careillo does not disclose, but Pratt discloses
wherein the first data is program data related to storage modes of the storage device and is capable of being read and executed by a host controller of the storage device to enable the host controller to support a storage mode corresponding to the first data, for changing the first storage mode of the storage device to a third storage mode (eg., 0026 - a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells that are dynamic SLCs, meaning the memory cells can be used in either of an SLC mode or a non-SLC mode (e.g., MLCs, TLCs, QLCs) and can be converted from one to the other ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello, with Pratt, providing the benefit of it can be beneficial to store data in an SLC mode to withstand higher temperatures and then return to using cells storing data in a non-SLC mode when temperatures fluctuate less or are more likely to be at a lower temperature (see Pratt, 0027) storage mode component resident on the memory sub-system (e.g., on the memory sub-system controller), to make it possible to control the storage mode of the memory sub-system (0014).
Claims 2, 3, 6, 11, 12, 13, 14, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20090193184) and in view of Cariello (US 20200210067) and Pratt (cited above) and further in view of Chen (US 20140359346) and Sun (US 20220365719)
Claim 2. Yu in view of Careillo and Pratt does not disclose, but Chen discloses
wherein the storage device comprises a storage block, the storage block comprises a plurality of data storage pages, and each of the data storage pages corresponds to a word line (eg., 0028 - control two pages, wherein the mapping relationship of the word lines and the pages can be referred to in FIG. 3);
the writing the first data into the storage device in the second storage mode corresponding to the first storage mode of the storage device comprises: writing the first data into a storage page corresponding to the target word line (eg., 0032 - controller 160 switches the access mode into the TLC mode from the SLC mode, and writes logic 1 (such as 0xFF) into the most-significant-bit page and the central-significant-bit page controlled by a first word line in the TLC mode to adjust the voltage distribution of the page controlled by the first word line in the SLC cell.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt with Chen, providing the benefit of an error correction method capable of adjusting the voltage distribution of the data storage device (see Chen, 0003) flash memory 180 of the present invention is capable of operating in different access mode (0026).
Yu in view of Careillo and Pratt and Chen does not disclose, but Sun discloses
determining at least one target word line from word lines of the data storage pages; writing the first data into at least one data storage page corresponding to the at least one target word line (eg., 0032 - programming data to or reading data from the target wordline).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt with Chen, with Sun providing the benefit of manage one or more operations of the data storage device (see Sun, 0031) improve the storing and reading log data and user data in a data storage device (0004).
Claim 11. (dependent from Claim 2) Yu discloses wherein the second storage mode is based on the first storage mode; a number of data states stored in the storage device corresponding to the second storage mode is less than that corresponding to the first storage mode (eg., [0050] FIGS. 2A-C show cell states in SLC and MLC flash memory. In FIG. 2A, a MLC flash cell has 4 states that are distinguished by different voltages generated when reading or sensing the cell. An erased 00 state has the lowest read voltage, while a fully programmed 11 state generates the largest read voltage. Two intermediate states 01 and 10 produce intermediate read voltages. Thus two binary bits can be stored in one MLC cell that has four states);
Yu in view of Careillo and Pratt and Chen does not disclose, but Sun discloses
a number of data states stored in the storage device corresponding to the third storage mode is less than that corresponding to the first storage mode.
(eg., 0036 - pSLC and pMLC refers to having a different memory cell capacity than the rest of the memory device. For example, if the first die 302a is a TLC memory device, each cell includes 3 bits. However, a pSLC block has 1 bit per cell and a pMLC has 2 bits per cell.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt with Chen, with Sun providing the benefit of manage one or more operations of the data storage device (see Sun, 0031) improve the storing and reading log data and user data in a data storage device (0004).
Claim 3. Yu does not disclose, but Careillo discloses
wherein the storage block further comprises at least one cache storage page; the writing the first data into at least one data storage page corresponding to the at least one target word line in the second storage mode comprises: writing configuration data into the at least one cache storage page in the second storage mode (eg., 0020 - if data written to the memory device will ultimately be stored in a TLC encoding, an SLC cache block can be used to quickly store the write data from the host);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello providing the benefit of a mixed encoding (see Cariello, 0023) to address the current need in the art to quickly store the write data from the host—because SLC writes are often much faster than MLC writes. This enables the host to move on to other tasks while the memory device takes the time it needs to transcribe that data to TLC blocks (e.g., in the background) for final storage (see Cariello, 0020).
Yu in view of Careillo and Pratt does not disclose, but Chen discloses
writing the first data into the at least one storage page corresponding to the at least one target word line based on the configuration data in the at least one cache storage page (eg., 0032 - controller 160 switches the access mode into the TLC mode from the SLC mode, and writes logic 1 (such as 0xFF) into the most-significant-bit page and the central-significant-bit page controlled by a first word line in the TLC mode to adjust the voltage distribution of the page controlled by the first word line in the SLC cell).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt with Chen, providing the benefit of an error correction method capable of adjusting the voltage distribution of the data storage device (see Chen, 0003) flash memory 180 of the present invention is capable of operating in different access mode (0026).
Claim 6. Yu does not disclose, but Careillo discloses
wherein the first storage mode is a TLC (Triple-level Cell) mode, the second storage mode is a pSLC (pseudo Single-Level Cell) mode, the writing configuration data into at least one cache storage page in the second storage mode comprises: writing the configuration data into the first cache storage page and the second cache storage page in the second storage mode (eg., 0023 - a pseudo SLC (pSLC) is described that can be used within an MLC block. The enables a switch from slow MLC writes (e.g., two-level MLC, TLC, QLC, etc.) to fast single level writes—pSLC);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello providing the benefit of a mixed encoding (see Cariello, 0023) to address the current need in the art to quickly store the write data from the host—because SLC writes are often much faster than MLC writes. This enables the host to move on to other tasks while the memory device takes the time it needs to transcribe that data to TLC blocks (e.g., in the background) for final storage (see Cariello, 0020).
Yu in view of Careillo and Pratt and Chen does not disclose, but Sun discloses
the at least one cache storage page comprises a first cache storage page, a second cache storage page, and a third cache storage page (eg., 0028 plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 may write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt with Chen, with Sun providing the benefit of manage one or more operations of the data storage device (see Sun, 0031) improve the storing and reading log data and user data in a data storage device (0004).
Claim 12 is rejected for reasons similar to Claim 2 above.
Claim 13 is rejected for reasons similar to Claim 11 above.
Claim 14 is rejected for reasons similar to Claim 3 above.
Claim 17 is rejected for reasons similar to Claim 6 above.
Claim 20 is rejected for reasons similar to Claim 2 above.
Claims 7, 8, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20090193184) and in view of Cariello (US 20200210067) and Pratt (cited above) and further in view of Chen (US 20140359346) and Sun (US 20220365719) and Linnen (US 20230106371 A1)
Claim 7. Yu in view of Careillo and Pratt and Chen does not disclose, but Sun discloses
and the at least one cache storage page comprises a first cache storage page, a second cache storage page, and a third cache storage page (eg., 0028 plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 may write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt with Chen, with Sun providing the benefit of manage one or more operations of the data storage device (see Sun, 0031) improve the storing and reading log data and user data in a data storage device (0004).
Yu in view of Careillo, and Pratt Chen and Sun does not disclose, but Linnen discloses
wherein the first storage mode is a TLC (Triple-level Cell) mode, the second storage mode is a pMLC (pseudo Multi-Level Cell) mode and (eg., 0033 - memory or more (e.g., QLC memory stores 4 bits per cell… a pseudo multi-level cell (pMLC) memory refers to a TLC memory that is used in a way that reduces the number of bits stored in each cell from three to two, which can increase the duration and reliability of the memory. As such, it may be desirable to store more-important data in pMLC memory than in TLC memory);
the writing configuration data into at least one cache storage page in the second storage mode comprises: writing the configuration data into the first cache storage page in the second storage mode (0033 - desirable to store more-important data in pMLC memory than in TLC memory.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello, and Pratt Chen and Sun with Linnen, providing the benefit of reduces the number of bits stored in each cell from three to two, which can increase the duration and reliability of the memory (see Linnen, 0033).
Claim 8. Yu in view of Careillo and Pratt and Chen does not disclose, but Sun discloses
wherein the first storage mode is a MLC (Multi-Level Cell) mode, the second storage mode is a pSLC (pseudo Single-Level Cell) mode (eg., 0036 - plurality of log blocks 306a-306d may be pseudo SLC (pSLC) or pseudo MLC (pMLC) log blocks. pSLC and pMLC refers to having a different memory cell capacity than the rest of the memory device. For example, if the first die 302a is a TLC memory device, each cell includes 3 bits. However, a pSLC block has 1 bit per cell and a pMLC has 2 bits per cell.)
the at least one cache storage page comprises a first cache storage page and a second cache storage page (eg., 0028 plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 may write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt with Chen, with Sun providing the benefit of manage one or more operations of the data storage device (see Sun, 0031) improve the storing and reading log data and user data in a data storage device (0004).
Yu in view of Careillo and Pratt and Sun does not disclose, but Linnen discloses
writing configuration data into at least one cache storage page in the second storage mode comprises: writing the configuration data into the first cache storage page in the second storage mode. (0033 - desirable to store more-important data in pMLC memory than in TLC memory.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello and Pratt and Sun with Linnen, providing the benefit of reduces the number of bits stored in each cell from three to two, which can increase the duration and reliability of the memory (see Linnen, 0033).
Claim 18 is rejected for reasons similar to Claim 7 above.
Claim 19 is rejected for reasons similar to Claim 8 above.
Response to Arguments
Applicant's arguments filed 2/9/2026 have been fully considered but they are not persuasive.
For claims 1, 9 and 10, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Yu in view of Careillo does not disclose, but Pratt discloses
wherein the first data is program data related to storage modes of the storage device and is capable of being read and executed by a host controller of the storage device to enable the host controller to support a storage mode corresponding to the first data, for changing the first storage mode of the storage device to a third storage mode (eg., 0026 - a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells that are dynamic SLCs, meaning the memory cells can be used in either of an SLC mode or a non-SLC mode (e.g., MLCs, TLCs, QLCs) and can be converted from one to the other ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the hybrid flash storage system as disclosed by Yu with Cariello, with Pratt, providing the benefit of it can be beneficial to store data in an SLC mode to withstand higher temperatures and then return to using cells storing data in a non-SLC mode when temperatures fluctuate less or are more likely to be at a lower temperature (see Pratt, 0027) storage mode component resident on the memory sub-system (e.g., on the memory sub-system controller), to make it possible to control the storage mode of the memory sub-system (0014).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1, 9 and 10, which are addressed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135