Response to Arguments
Applicant's arguments filed 06/23/2026have been fully considered but they are not persuasive.
Applicant argued that Lai fails to disclose the feature “the shift sub-circuit is provided with a third node at all, such that a control electrode of the at least one drive circuit output transistor M6 or M7 is electrically connected with the third node through the at least one transistor of the second control part 20 (allegedly corresponding to "the output sub-circuit"), and a control electrode of the at least one shift output transistor M17 is electrically connected with the third node through the at least one transistor of the first control part 10, which is incorrect. See FIGS. 5, 7, 9, and 11, the sixth control unit 103 includes a twelfth transistor M12 and a thirteenth transistor M13, where a source of the twelfth transistor M12 is connected to the second voltage signal VGL1, a drain of the twelfth transistor M12 is connected to the third node N3, and a gate of the twelfth transistor M12 is connected to the first node N1; and a source of the thirteenth transistor M13 is connected to the first voltage signal VGH1, a drain of the thirteenth transistor M13 is connected to the third node N3, and a gate of the thirteenth transistor M13 is connected to the second node N2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 13-16 1is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lai et al. (US 2002/0076618).
Regarding claim 1, Lai et al. (US 2002/0076618), figs. 2-11, discloses a shift register, comprising: a shift sub-circuit and an output sub-circuit; wherein the shift sub-circuit is electrically connected with a signal input terminal, first clock a second clock signal terminal (CK), a first power supply terminal (VGH1), a second power supply terminal (VGL1), and a cascaded signal output terminal respectively, and is configured to provide a signal to the cascaded signal output terminal under control of signals of the signal input terminal (Provided are a display panel and a display device. The display panel includes a driving circuit. The driving circuit includes N stages of cascaded shift registers), the first clock signal terminal, the second clock signal terminal, the first power supply terminal, and the second power supply terminal; the output sub-circuit is electrically connected with the shift sub-circuit, a latch signal terminal, a first control signal terminal, a second control signal terminal, a third power supply terminal, a fourth power supply terminal, a fifth power supply terminal, the cascaded signal (FIGS. 5 and 6, in an embodiment, the first control unit 201 includes a first transistor M1 and a second transistor M2. One terminal of the first transistor M1 is connected to the third node N3, another terminal of the first transistor M1 is connected to the fourth node N4, and a control terminal of the first transistor M1 is connected to a frequency control signal terminal and is configured to receive the frequency control signal CRL. One terminal of the second transistor M2 receives the third voltage signal VG11, another terminal of the second transistor M2 is connected to the fourth node N4, and a control terminal of the second transistor M2 is connected to the frequency control signal terminal and is configured to receive the frequency control signal CRL), and a drive signal output terminal respectively, and is configured to provide a signal to the drive signal output terminal under control of signals of the shift sub-circuit, the latch signal terminal, the first control signal terminal, the second control signal terminal, the cascaded signal output terminal, the third power supply terminal, the fourth power supply terminal, and the fifth power supply terminal (As shown in FIGS. 5 and 6, in an embodiment, the first control unit 201 includes a first transistor M1 and a second transistor M2. One terminal of the first transistor M1 is connected to the third node N3, another terminal of the first transistor M1 is connected to the fourth node N4, and a control terminal of the first transistor M1 is connected to a frequency control signal terminal and is configured to receive the frequency control signal CRL. One terminal of the second transistor M2 receives the third voltage signal VG11, another terminal of the second transistor M2 is connected to the fourth node N4, and a control terminal of the second transistor M2 is connected to the frequency control signal terminal and is configured to receive the frequency control signal CRL); the shift sub-circuit comprises: at least one shift output transistor, the shift output transistor is electrically connected with the cascaded signal output terminal, and the output sub- circuit comprises: at least one drive output transistor, and the drive output transistor is electrically connected with the drive signal output terminal (see pars. 143, 146, 147); the shift sub-circuit further comprises: at least one transistor, and the output sub-circuit further comprises: at least one transistor; the shift sub-circuit is provided with a third node (see fig. 6, output terminal), a control electrode of the at least one drive output transistor is electrically connected with the third node through the at least one transistor of the output sub-circuit (When the first transistor M1 is turned on in response to the frequency control signal CRL, the conductance between the third node N3 connected to one terminal of the first transistor M1 and the fourth node N4 connected to another terminal of the first transistor M1 is achieved), and a control electrode of the at least one shift output transistor is electrically connected with the third node through the at least one transistor of the shift sub-circuit (FIGS. 7 and 8, each of the first transistor M1 and the third transistor M3 is an NMOS type transistor, and each of the second transistor M2 and the fourth transistor M4 is a PMOS type transistor. When the frequency control signal CRL is at a high level, the first transistor M1 is turned on, the signal of the third node N3 is transmitted to the fourth node N4, the second transistor M2 is turned off, the third transistor M3 is turned on, the signal of the second node N2 is transmitted to the fifth node N5, and the fourth transistor M4 is turned off. In this case, the signal of the fourth node N4 is the signal of the third node N3, the signal of the fifth node N5 is the signal of the second node N2, and the output signal OUT generated by the second control part 20 is determined by the signal of the third node N3 and the signal of the second node N2 controlled by the first control part 10. When the frequency control signal CRL is at a low level, the first transistor M1 is turned off, the second transistor M2 is turned on, the third voltage signal VG11 is transmitted to the fourth node N4, the third transistor M3 is turned off, the fourth transistor M4 is turned on, and the fourth voltage signal VG22 is transmitted to the fifth node N5. In this case, the signal of the fourth node N4 is the third voltage signal VG11, the signal of the fifth node N5 is the fourth voltage signal VG22, and the output signal OUT generated by the second control part 20 is determined by the third voltage signal VG11 and the fourth voltage signal VG22. In this manner, it is achieved that the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 control the signal of the fourth node N4 and the signal of the fifth node N5 under the control of the same frequency control signal CRL, and no additional frequency control signal is required, which is conducive to simplifying the circuit structure of the shift register 200 and reducing the complexity of the shift register 200).
Regarding claim 2, Lai et al. (US 2002/0076618), figs. 2-6, discloses a the shift register according to claim 1, wherein the shift sub-circuit is further electrically connected with the fifth power supply terminal, and is configured to provide a signal to the cascaded signal output terminal under control of signals of the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, and the fifth power supply terminal (The third control unit 203 of the second control part 20 generates an output signal OUT based on the fifth voltage signal VGH3. The potential of one of the third voltage signal VG11 or the fourth voltage signal VG22 which is a high level signal is equal to the potential of the first voltage signal VGH1 or equal to the potential of the fifth voltage signal VGH3, that is, the first voltage signal VGH1 is multiplexed into one of the third voltage signal VG11 or the fourth voltage signal VG22 which is a high level signal, or the fifth voltage signal VGH3 is multiplexed into one of the third voltage signal VG11 or the fourth voltage signal VG22 which is a high level signal. In this manner, the arrangement of signals and wiring can be reduced, which is conducive to simplifying the circuit structure of the shift register 200 and reducing the complexity of the shift register 200).
Regarding claim 13, Lai et al. (US 2002/0076618), figs. 2-6, discloses the shift register according to claim 1, wherein the first power supply terminal and the third power supply terminal are a same signal terminal, and the second power supply terminal and the fourth power supply terminal are a same signal terminal (With reference to FIGS. 2 and 3, the shift register 200 in the driving circuit 100 includes the first control part 10 and the second control part 20. The first control part 10 controls the signal of the second node N2 and the signal of the third node N3 based on the input signal IN, the first clock signal CK, the first voltage signal VGH1, and the second voltage signal VGL1. The first control unit 201 and the second control unit 202 of the second control part 20 controls the signal of the fourth node N4 and the signal of the fifth node N5 based on the third voltage signal VG11, the fourth voltage signal VG22, and the signal of the second node N2 and the signal of the third node N3 controlled by the first control part 10 and in response to the frequency control signal CRL. The third control unit 203 of the second control part 20 generates an output signal OUT based on the fifth voltage signal VGH3 and the sixth voltage signal VGL3 and in response to the signal of the fourth node N4 and the signal of the fifth node N5. That is, the first control part 10 and the first control unit 201 and the second control unit 202 of the second control part 20 are the control part of the shift register 200 and play a control role; and the third control unit 203 of the second control part 20 is the output part of the shift register 200 and is configured to generate the output signal OUT).
Regarding claims 14-15, Lai et al. (US 2002/0076618), figs. 2-6, discloses the gate drive circuit, comprising a plurality of shift registers according to claim 1; wherein a cascaded signal output terminal of one shift register in at least one stage shift register is electrically connected with a signal input terminal of a previous stage shift register (see FIG. 1 is a structure diagram of a display panel according to an embodiment of the present disclosure, FIG. 2 is a structure diagram of a driving circuit according to an embodiment of the present disclosure, FIG. 3 is a structure diagram of a shift register according to an embodiment of the present disclosure, and FIG. 4 is a structure diagram of another shift register according to an embodiment of the present disclosure. As shown in FIGS. 1 to 4, the display panel provided in the embodiment of the present disclosure includes a driving circuit 100. The driving circuit 100 includes N stages of cascaded shift registers 200, where N≥2. The shift register 200 includes a first control part 10 and a second control part 20. The first control part 10 receives at least an input signal IN and controls a signal of a first node N1 and a signal of a second node N2 in response to at least a first clock signal CK, and the first control part 10 receives a first voltage signal VGH1 and a second voltage signal VGL1 and controls a signal of a third node N3 in response to a signal of the first node N1 and a signal of the second node N2, where the first voltage signal VGH1 is a high level signal, and the second voltage signal VGL1 is a low level signal. The second control part 20 includes a first control unit 201, a second control unit 202, and a third control unit 203).
Regarding claim 16, Lai et al. (US 2002/0076618), figs. 2-6, discloses the drive method of a shift register, configured to drive the shift register according to claim 1, wherein the method comprises: providing a signal to a cascaded signal output terminal by a shift sub-circuit under control of signals of a signal input terminal, a first clock signal terminal, a second clock signal terminal, a first power supply terminal, and a second power supply terminal; and providing a signal to a drive signal output terminal by an output sub-circuit under control of signals of the shift sub-circuit, a latch signal terminal, a first control signal terminal, a second control signal terminal, the cascaded signal output terminal, a third power supply terminal, a fourth power supply terminal, and a fifth power supply terminal (In a T2 stage, the input signal IN is at a high level, the first clock signal CK is at a high level. FIGS. 5 to 12, in an embodiment, to ensure the stability of the potentials of the second node N2 and the third node N3 and the stability of the output signal OUT, the second control part 20 further includes a first capacitor C1 and a second capacitor C2. A first electrode plate of the first capacitor C1 is connected to the fifth voltage signal VGH3).
Allowable Subject Matter
Claims 3-12, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the references cited in record disclose or suggest The shift register according to claim 2, wherein the shift sub-circuit comprises: a first transistor to a sixteenth transistor and a first capacitor to a third capacitor; a control electrode of the first transistor is electrically connected with the first clock signal terminal, a first electrode of the first transistor is electrically connected with the signal input terminal, and a second electrode of the first transistor is electrically connected with the third node; a control electrode of the second transistor is electrically connected with the third node, a first electrode of the second transistor is electrically connected with the first clock signal terminal, and a second electrode of the second transistor is electrically connected with a tenth node; a control electrode of the third transistor is electrically connected with the first clock signal terminal, a first electrode of the third transistor is electrically connected with the second power supply terminal, and a second electrode of the third transistor is electrically connected with the tenth node; a control electrode of the fourth transistor is electrically connected with a second node, a first electrode of the fourth transistor is electrically connected with the second clock signal terminal, and a second electrode of the fourth transistor is electrically connected with a fifth node; a control electrode of the fifth transistor is electrically connected with the tenth node, a first electrode of the fifth transistor is electrically connected with the first power supply terminal, and a second electrode of the fifth transistor is electrically connected with the fifth node; a control electrode of the sixth transistor is electrically connected with a sixth node, a first electrode of the sixth transistor is electrically connected with the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected with a first node; a control electrode of the seventh transistor is electrically connected with the second clock signal terminal, a first electrode of the seventh transistor is electrically connected with the first node, and a second electrode of the seventh transistor is electrically connected with a fourth node; a control electrode of the eighth transistor is electrically connected with the third node, a first electrode of the eighth transistor is electrically connected with the first power supply terminal, and a second electrode of the eighth transistor is electrically connected with the fourth node; a control electrode of the ninth transistor is electrically connected with the fourth node, a first electrode of the ninth transistor is electrically connected with the first power supply terminal, and a second electrode of the ninth transistor is electrically connected with the cascaded signal output terminal; a gate electrode of the tenth transistor is electrically connected with a ninth node, a first electrode of the tenth transistor is electrically connected with the second power supply terminal, and a second electrode of the tenth transistor is electrically connected with the cascaded signal output terminal; a control electrode of the eleventh transistor is electrically connected with the second power supply terminal, a first electrode of the eleventh transistor is electrically connected with the tenth node, and a second electrode of the eleventh transistor is electrically connected with the sixth node; a control electrode of the twelfth transistor is electrically connected with the second power supply terminal, a first electrode of the twelfth transistor is electrically connected with the third node, and a second electrode of the twelfth transistor is electrically connected with the ninth node; a control electrode of the thirteenth transistor is electrically connected with the fifth power supply terminal, a first electrode of the thirteenth transistor is electrically connected with the first power supply terminal, and a second electrode of the thirteenth transistor is electrically connected with the third node; a control electrode of the fourteenth transistor is electrically connected with the first clock signal terminal, a first electrode of the fourteenth transistor is electrically connected with the signal input terminal, and a second electrode of the fourteenth transistor is electrically connected with a first electrode of the fifteenth transistor; a control electrode of the fifteenth transistor is electrically connected with the second power supply terminal, and a second electrode of the fifteenth transistor is electrically connected with the second node; a control electrode of the sixteenth transistor is electrically connected with the second node, a first electrode of the sixteenth transistor is electrically connected with the ninth node, and a second electrode of the sixteenth transistor is electrically connected with the second node; a first electrode plate of the first capacitor is electrically connected with the sixth node, and a second electrode plate of the first capacitor is electrically connected with the first node; a first electrode plate of the second capacitor is electrically connected with the fourth node, and a second electrode plate of the second capacitor is electrically connected with the first power supply terminal; and a first electrode plate of the third capacitor is electrically connected with the second node, and a second electrode plate of the third capacitor is electrically connected with the fifth node.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VAN N CHOW/ Primary Examiner, Art Unit 2627
Prosecution Insights