DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 06/26/2026, for application number 18/851,838 has been received and entered into record. Claims 1-3, 6, 8, 9, 11, 13 and 14 are amended. Claim 7 has been cancelled. Claims 16-21 have been added. Thus, claims 1-6, 8-21 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Han (US 2019/0369656 A1) in view of Branover et al. (US 2013/0246820 A1).
Regarding claim 1, Han teaches a non-transitory machine-readable medium comprising instructions that, when executed by a processor (Figures 2 and 4), cause the processor to:
set a target frequency of a central processing unit (CPU) (“the working frequency and the working voltage of the multi-core CPU 11 are then adjusted, which are adjusted to the working frequency and the working voltage defined by the overclocking numerical data.” Par 0033 and Figure 1, step 14); and
if the first operating frequency is lower than the target frequency by a margin due to thermal throttling and a CPU thermal condition had been met, then store the first operating frequency and the second operating frequency for overclock operation of the CPU, otherwise repeat the benchmarking the CPU for the target frequency set with an increased value and the determining the first operating frequency and the second operating frequency until the first operating frequency is lower than the target frequency of the increased value by the margin due to thermal throttling and the CPU thermal condition is met (“if a determination is made that the … working temperature of the multi-core CPU 11 … have exceeded the … maximum temperature limit of the multi-core CPU 11, then an action of order reduction [margin] is performed with the working frequency and the working voltage of the overclocking numerical data as the benchmark, and the overclocking numerical data of the working frequency and the working voltage after the order reduction is revealed on the BIOS 12, which is available for a user to choose whether to adopt the overclocking numerical data” par 0017 and “if a determination is made that the … working temperature of the multi-core CPU 11 presented after the heavy load test have not exceeded the … maximum temperature limit of the multi-core CPU 11, that is to say, the overclocking numerical data thereof cannot achieve the optimized overclocking effect, then the working frequency … is retrieved to perform adjustment, and the working frequency and the working voltage defined by the corresponding overclocking numerical data are used as a benchmark, and the working frequency and the working voltage of the multi-core CPU 11 are then adjusted, which are adjusted to the working frequency … defined by the overclocking numerical data [target frequency], … until the … the working temperature presented have exceeded the … maximum temperature limit of the multi-core CPU 11,” par 0018 and Fig. 1) [this iterative process increases frequencies against thermal limits, reduces frequency once the limit is met and reveals (outputs/stores) stable data for the user to apply for overclocking].
However, Han does not explicitly teach benchmark the CPU for the target frequency under a first load and a second load, wherein the first load is lighter than the second load; based on the benchmarking, determine a first operating frequency of the CPU under the first load and a second operating frequency of the CPU under the second load.
In the analogous art, Branover teaches benchmark the CPU for the target frequency under a first load and a second load (“Power management unit 20 may also set the operating point of a given processing node based on a particular type of workload… a processor core 11 executing a compute-bounded workload may be set to a higher operating point, or to a lower operating point when executing a memory-bounded workload.” Par 0045), wherein the first load is lighter than the second load (“Power management unit 20 in one embodiment may cause a processor core 11 to operate at P-state P0 responsive to a high activity level” par 0048 and “ Power management unit 20 may cause a processor core 11 to operate in P-state P4 responsive to a low activity level,” par 0049 and par 48, Table 1) [the first workload may correspond to the memory-bounded workload and second workload may correspond to the compute-bounded workload; the low-activity level maps to the memory-bounded workload and high activity level maps to the compute-bounded workload];
based on the benchmarking, determine a first operating frequency of the CPU under the first load and a second operating frequency of the CPU under the second load (“Power management unit 20 may also set the operating point of a given processing node based on a particular type of workload… a processor core 11 executing a compute-bounded workload may be set to a higher operating point, or to a lower operating point when executing a memory-bounded workload.” Par 0045 and “compute-bounded workloads having a high activity level may be executed in P-state P0 [highest point], which may enable faster completion.” Par 0048 and “P-state P4 [lowest point] may be used with memory-bounded workloads as well as with other tasks that are not time-sensitive (or frequency-sensitive).” Par 0049 and par 48, Table 1) [the memory bound workload maps to an operating frequency of 800 MHz in the P4 state and the compute bound workload maps to an operating frequency of 2 GHz in the P0 state as shown in table 1, par 48].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Han and Branover before him before the effective filing date of the claimed invention, to have modified Han to incorporate the teachings of Branover to have different operating frequencies for different types of workloads to have minimal performance impact with power savings to improve performance-per-watt metric of the system for lighter loads and enable faster completion for computationally-intensive workloads. (Branover, paragraphs 48, 49)
Regarding claim 2, Han and Branover teach the non-transitory machine-readable medium of claim 1. Branover further teaches wherein the instructions are to:
determine the first operating frequency as a first maximum frequency from the benchmarking under the first load (“Limiting an operating point may be defined as limiting the clock frequency and/or operating voltage to specified maximum values for particular set of conditions (but not necessarily maximum limits for all conditions)” par 0027 and “a processor core 11 executing a compute-bounded workload may be set to a higher operating point, or to a lower operating point when executing a memory-bounded workload.” Par 0045 and par 48 Table 1); and
determine the second operating frequency as a second maximum frequency from the benchmarking under the second load (“compute-bounded workloads having a high activity level may be executed in P-state P0, which may enable faster completion.” Par 0048 and “it may thus be increased to such a point as to enable overclocking, i.e. running its corresponding clock signal at a frequency higher than specified” par 0030 and par 48 Table 1) [the clock speed limit (P4 at 800 MHz) is the first maximum frequency for lighter memory bound workloads; the clock speed limit (P0 at 2 GHz) is the second maximum frequency for compute bound workloads].
Regarding claim 4, Han and Branover teach the non-transitory machine-readable medium of claim 1. Branover further teaches wherein the CPU thermal condition comprises:
a CPU temperature exceeding a threshold temperature; or a thermal throttling of the CPU exceeding a threshold thermal throttling (“The control logic within the power management unit 20 may throttle a given processing node in response to detecting a temperature reading from a sensor near or within the given processing node exceeds a respective threshold.” Par 0100 and “Responsive to determining a count of throttling exceeds a first threshold within a time interval for the given processing node, the control logic within the power management unit 20 may reduce the power limit for the given processing node.” Par 0101) [the control loop reacts both to a specific temperature threshold being exceeded and to the monitored amount of thermal throttling exceeding a limit].
Regarding claim 18, Han and Branover teach the non-transitory machine-readable medium of claim 1. Han further teaches wherein the instructions are to iteratively update and store a running maximum of the first operating frequency and a running maximum of the second operating frequency over a plurality of target frequencies (“Step S162: if not beyond the limits, retrieving other overclocking numerical data to adjust the working frequency and the working voltage… until the working frequency, the working voltage, and the working temperature presented have exceeded the maximum frequency limit… the smart overclocking method achieves the efficacy of automatic evaluation of a thermal dissipation environment and offer of the optimized proposal for overclocking.” par 0018 and “the overclocking database 121 has multiple overclocking numerical data, and … respective overclocking numerical data define working frequency … every core in every multi-core CPU 11 has different operational efficacy, and even with a same number of core units, different models of multi-core CPUs 11 can also correspond to the different highest overclocking levels.” Par 0011) [first and second maximum frequencies correspond to highest stable clock speeds for first and second loads’ target frequencies are retrieved from the database and tested during search for the maximum frequencies].
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Han and Branover in view of Berry Jr. et al. (US 2015/0057975 A1).
Regarding claim 3, Han and Branover teach the non-transitory machine-readable medium of claim 2. However, Han and Branover do not explicitly teach wherein: the first maximum frequency is a maximum over a set of target frequencies of the CPU used in the benchmarking; and the second maximum frequency is a maximum over the set of target frequencies of the CPU used in the benchmarking.
In the analogous art, Berry Jr. teaches the first maximum frequency is a maximum over a set of target frequencies of the CPU used in the benchmarking (“Starting at the nominal operating frequency, the existing frequency guard banding procedures either execute a binary search algorithm or sequentially increment the operating frequency of the processor to determine the maximum operating frequency before which system failure is detected” par 0011); and
the second maximum frequency is a maximum over the set of target frequencies of the CPU used in the benchmarking (“The validation analysis unit 106 can then execute operations described above at stage D and stage E to determine the actual system maximum operating frequency associated with the processor 122” par 0022 and Figure 1) [the benchmarking operations are repeated for a second load to determine its specific maximum stable frequency over the set of frequencies tested in that iteration].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Han, Branover and Berry Jr. before him before the effective filing date of the claimed invention, to have modified Han and Branover to incorporate the teachings of Berry Jr. because all references are directed at adjusting frequencies of different workloads to achieve optimized performance. Having the first and second maximum frequencies determined over a set of frequencies used in benchmarking reduces time and computational resources to ensure a processor is operating as expected. (Berry Jr. paragraph 53)
Regarding claim 5. Han and Branover teach the non-transitory machine-readable medium of claim 1. However, Han and Branover do not explicitly teach wherein the margin is between 10% and 20%.
In the analogous art, Berry Jr. teaches wherein the margin is between 10% and 20% (“if a frequency guard band that is 15% higher than the nominal operating frequency is desired, the validation analysis unit 106 may halt the frequency guard band validation process when the operating frequency is at least 15% higher than the nominal operating frequency.” Par 0024).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Han, Branover and Berry Jr. before him before the effective filing date of the claimed invention, to have modified Han and Branover to incorporate the teachings of Berry Jr. because all references are directed at adjusting frequencies of different workloads to achieve optimized performance. Having a margin between 10% and 20%, as taught in Berry Jr. with the frequency guard band being 15%, provides a safety buffer to ensure the processor operates normally and achieves desired performance levels even when environmental or system changes (temperature change, system glitches, etc.) occur and reduce the overall validation cycle time.
Claims 6, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. in view of Yan et al. (US 2022/0113757 A1).
Regarding claim 6, Berry Jr. teaches a device comprising:
a central processing unit (CPU) (Figure 1, processor 122);
storage connected to the CPU (Figure 6, memory unit 606 and paragraph 15), the storage including executable instructions to:
iterate over a series of increasing target clock frequencies for the CPU (“The validation analysis unit 106 can increment (at regular intervals) the operating frequency of the processor 122 … For example, beginning at the validation start frequency, the validation analysis unit 106 can increment the operating frequency of the processor 122 by 1% of the validation start frequency at each iteration.” Par 0020);
for each of one or more clock frequencies of the series of increasing target clock frequencies, initiate execution of different test loads by the CPU (“Each of the test workloads may be associated with distinct workload characteristics and may be designed to stress various components of the system at different levels, to stress the processor at different levels,” par 0028 and “the validation analysis unit 106 can increment the operating frequency of the processor 122 by 1% of the validation start frequency at each iteration.” Par 0020 and Figure 2) and store a maximum operating frequency of the CPU for each test load of the different test loads (“The validation analysis unit 106 can store an indication of the system maximum operating frequency and the system parametric data at the system maximum operating frequency in the system parametric data store 108.” Par 0020 and “The system parametric data store 108 can also comprise an indication of a system configuration associated with the system 120 on which the processors were previously validated, workload(s) that was executed by the previously validated processors to generate the system parametric data” par 0013 and Figure 1).
However, Berry Jr. does not explicitly teach determine that a condition of the CPU has been reached based on detecting that the maximum operating frequency of the CPU under a lowest test load of the different test loads is below a threshold frequency due to thermal throttling; when the condition of the CPU has been reached, cease iteration over the series of increasing target clock frequencies and overclock the CPU based on the maximum operating frequency of the CPU for each test load.
In the analogous art, Yan teaches determine that a condition of the CPU has been reached based on detecting that the maximum operating frequency of the CPU under a lowest test load of the different test loads is below a threshold frequency due to thermal throttling (“the trial evaluation circuitry 208 identifies the trial as a failure because the values of the overclocking parameters selected by the optimization model 216 for the trial caused the temperature of the processing unit 102 to increase beyond an allowable threshold for performing overclocking.” Par 0047 and “at block 318, the cooler monitoring circuitry 204 determines that the temperature of the processing unit 102 has not been reduced within a threshold amount of time, the cooler monitoring circuitry 204 identifies the trial as a failure because the selected overclocking parameter values increased the temperature of the processing unit 102 and introduced a risk of overheating.” Par 0071 and “The trial scores are used to identify the optimal overclocking parameter values that provide for the greatest increase of the clock rate” par 0017 and par 41, 48, 50) [an iterative trail is determined to be a failure when selected frequency and voltage parameters cause CPU to exceed the threshold];
when the condition of the CPU has been reached, cease iteration over the series of increasing target clock frequencies and overclock the CPU based on the maximum operating frequency of the CPU for each test load (“the trial evaluation circuitry 208 identifies the trial as a failure because the values of the overclocking parameters selected by the optimization model 216 for the trial caused the temperature of the processing unit 102 to increase beyond an allowable threshold for performing overclocking.” Par 0047 and “The trial control circuitry 206 continues to cause trials to be performed until the number of trials performed and/or the duration of time for the experiment satisfies the tuning budget for the experiment.” Par 0050 and “ the clock rate tuning circuitry 112 outputs the optimal values of the overclocking parameters (e.g., voltage, temperature threshold, core ratio, etc.) for the processing unit 102 as determined from the experiment to increase the clock rate of processing unit 102 while maintaining or promoting stability of the processing unit 102 …the clock rate tuning circuitry 112 causes the processing unit 102 to automatically implement the optimal parameters” Par 0031) [the iterative process ends when a tuning budget is reached to apply the optimal values (including frequency) among the test loads].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr. and Yan before him before the effective filing date of the claimed invention, to have modified Berry Jr. to incorporate the teachings of Yan to identify the optimal overclocking parameters that provide the greatest increase of the clock rate while maintaining stability of the processor to maximize system performance and ensure the CPU doesn’t exceed thermal limits or become unstable.
Regarding claim 9, Berry Jr. and Yan teach the device of 6. Yan further teaches wherein the instructions are to determine that the condition of the CPU has been reached further based on:
detecting a CPU temperature exceeding a threshold temperature, or detecting thermal throttling of the CPU exceeding a threshold thermal throttling (“the trial evaluation circuitry 208 identifies the trial as a failure because the values of the overclocking parameters selected … caused the temperature of the processing unit 102 to increase beyond an allowable threshold for performing overclocking.” Par 0047 and par 48).
Regarding claim 10, Berry Jr. and Yan teach the device of claim 6. Yan further teaches wherein the instructions are to increase CPU voltage when increasing a clock frequency for the CPU (“processing unit 102 of FIG. 1 can be overclocked to increase the clock rate of the processing unit 102 … the clock rate tuning circuitry 112 determines parameter values such as core voltage … to overclock the processing unit 102 ” par 0023) [the tuning circuit sets specific core voltage values to facilitate increasing the processor’s clock rate during overclocking].
Claims 12, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. in view of Han.
Regarding claim 12, Berry Jr. teaches the method of claim 11. However, Berry Jr. does not explicitly teach wherein determining whether the condition of the CPU has been reached further includes determining the CPU to be at an elevated thermal state.
In the analogous art, Han teaches wherein determining whether the condition of the CPU has been reached further includes determining the CPU to be at an elevated thermal state (“Step S16: reading in real time the working frequency, the working voltage, and the working temperature of the multi-core CPU and determining whether they have exceeded limits or not… a determination whether the working frequency, the working voltage, and the working temperature have exceeded the maximum frequency limit, the maximum voltage limit, and the maximum temperature limit of the multi-core CPU 11 is made.” par 0016) [the monitoring step checks if the CPU exceeding the limits by verifying if the real time temperature has reached elevated state beyond the threshold].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr. and Han before him before the effective filing date of the claimed invention, to have modified Berry Jr. to incorporate the teachings of Han to check whether the CPU is at an elevated thermal state to automatically evaluate the thermal environment and determine an optimized solution for overclocking. (Han, paragraph 18)
Regarding claim 13, Berry Jr. teaches the method of claim 11. However, Berry Jr. does not explicitly teach further comprising, when increasing the target frequency of the CPU, increasing a voltage of the CPU if the voltage is below a safe operating voltage for the increased target frequency.
In the analogous art, Han teaches when increasing the target frequency of the CPU, increasing a voltage of the CPU if the voltage is below a safe operating voltage for the increased target frequency (“the overclocking numerical data are secure overclocking numerical values and stable overclocking voltage numerical values, that is, different multi-core CPUs 11 have different most preferred overclocking numerical values, and respective multi-core CPU 11 has corresponding overclocking numerical data, while respective overclocking numerical data define working frequency and working voltage thereof,” par 0011 and “performing adjustment of the frequency and the voltage … which are adjusted to the working frequency and the working voltage defined by the overclocking numerical data.” Par 0014) [a database of secure and stable values is used to ensure the CPU voltage is adjusted to a safe level corresponding to the target frequency increase during the overclocking].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr. and Han before him before the effective filing date of the claimed invention, to have modified Berry Jr. to incorporate the teachings of Han to increase the voltage if it is below a safe operating voltage to improve system performance and achieve cost-effectiveness. (Han, paragraph 2)
Claim 19 corresponds to claim 13 and is rejected accordingly.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. in view of Branover.
Regarding claim 15, Berry Jr. teaches the method of claim 11. However, Berry Jr. does not explicitly teach further comprising activating different processing cores of the CPU to establish the first load and the second load.
In the analogous art, Branover teaches activating different processing cores of the CPU to establish the first load and the second load (“if all four processing nodes 11 are active and processing a workload, their respective local power limits may be set to equal values. However, if two processing nodes 11 are active while the other two are in an idle state, the local power limits for the active nodes may be increased with the local power limits for the idle nodes may be decreased correspondingly.” Par 0038 and Figure 1) [this shows establishing different loads by varying number of active cores].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr. and Branover before him before the effective filing date of the claimed invention, to have modified Berry Jr. to incorporate the teachings of Branover to reallocate power and thermal budgets from idle cores to active ones to enable higher performance and overclocking boosts while maintain the system within its global power limit. (Branover, paragraph 38)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Han and Branover in view of Ragland et al. (US 2021/0109562 A1).
Regarding claim 16, Han and Branover teach the non-transitory machine-readable medium of claim 1. However, Han and Branover do not explicitly teach wherein benchmarking the CPU under the first load and the second load comprises activating a first number of processing cores of the CPU to establish the first load and activating a second number of processing cores of the CPU to establish the second load, wherein the second number is greater than the first number.
In the analogous art, Ragland teaches wherein benchmarking the CPU under the first load and the second load comprises activating a first number of processing cores of the CPU to establish the first load and activating a second number of processing cores of the CPU to establish the second load (“The preferences may be on an individual core basis or based on a group and/or number of active cores (e.g., if 1 core is active, apply first overclocking preferences; if 2 cores are active, apply second overclocking preferences; etc.)… the example power control unit 106 obtains temperature(s) from the sensor(s) 104 and/or determines how many of the example core(s) 102 are active and compares the obtained data to the overclock configurations defined by the user and/or manufacturer preferences to determine how to dynamically adjust the clocking frequency” par 0021 and Figure 1) [different overclocking configurations (first and second preferences) are applied based on active cores corresponding to different loads for the CPU], wherein the second number is greater than the first number (e.g., if 1 core is active, apply first overclocking preferences; if 2 cores are active, apply second overclocking preferences; etc.) par 0021 [the first number corresponds to 1 core being active and second number corresponds to 2 cores being active].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Han and Branover and Ragland before him before the effective filing date of the claimed invention, to have modified Han and Branover to incorporate the teachings of Ragland to activate certain number of cores based on the load to enable the system to toggle between overclocked clock rates and operate at an increased speed without exceeding a maximum temperature. (Ragland, paragraph 14)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Han and Branover in view of Van Cleve et al. (US 2020/0159303 A1).
Regarding claim 17, Han and Branover teach the non-transitory machine-readable medium of claim 1. However, Han and Branover do not explicitly teach wherein the instructions are to determine the first operating frequency and the second operating frequency as sustained operating frequencies over a duration of the benchmarking based on at least one of a time-averaged frequency or a moving-averaged frequency.
In the analogous art, Van Cleve teaches wherein the instructions are to determine the first operating frequency and the second operating frequency as sustained operating frequencies over a duration of the benchmarking based on at least one of a time-averaged frequency or a moving-averaged frequency (“the machine-readable storage medium includes instructions to determine core and un-core operating frequency variations… a base core operating frequency and a base un-core operating frequency for each one of the two or more processors.” par 0016 and “monitoring unit 110 stores an averaged value, e.g., a running average, of the data.” Par 0024 and “Monitoring unit 110 may perform a power burn test … monitoring unit 110 performs burn tests that makes the processor execute at the operating frequency limit allowed by the power consumption limit.” Par 0025 and “During the power burn test, monitoring unit 110 may engage each one of the processors 102A, 102B, 102C, 102D, and 102E, one by one, in exhaustive operations. During the exhaustive operations, the respective registers of each processor is changed to indicate a change in the power consumption limit of the processor.” Par 0024) [the power burn tests (benchmarking) measures and stores the running average of core and uncore (first and second frequencies) to identify performance variations].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr., Yan and Van Cleve before him before the effective filing date of the claimed invention, to have modified Berry Jr. and Yan to incorporate the teachings of Van Cleve to have a running averaged frequency to ensure consistent and deterministic performance of the processor across various workloads. (Van Cleve, paragraph 41)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. and Yan in view of Van Cleve et al. (US 2020/0159303 A1).
Regarding claim 20, Berry Jr. and Yan teach the device of claim 6. However, Berry Jr. and Yan do not explicitly teach wherein the maximum operating frequency of the CPU for each test load is determined as a sustained operating frequency during execution of the respective test load based on at least one of a time-averaged frequency or a moving-averaged frequency.
In the analogous art, Van Cleve teaches wherein the maximum operating frequency of the CPU for each test load is determined as a sustained operating frequency during execution of the respective test load based on at least one of a time-averaged frequency or a moving-averaged frequency (“control units 120A, 120B, 120C, 120D, and 120E store the operating frequency of the respective processor, e.g., an average of the operating frequency, in the respective registers 118A, 118B, 118C, 118D, and 118E.” par 0020 and “monitoring unit 110 stores an averaged value, e.g., a running average, of the data.” Par 0024 and par 13, 21, 25) [the operating frequency is determined by executing processors at their frequency limit during tests and recording a running average].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr., Yan and Van Cleve before him before the effective filing date of the claimed invention, to have modified Berry Jr. and Yan to incorporate the teachings of Van Cleve to have a running averaged frequency to ensure consistent and deterministic performance of the processor across various workloads. (Van Cleve, paragraph 41)
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. in view of Van Cleve et al. (US 2020/0159303 A1).
Regarding claim 21, Berry Jr. teaches the method of claim 11, wherein the first maximum operating frequency and the second maximum operating frequency are determined as time-averaged operating frequencies or moving-averaged operating frequencies obtained over a duration of the stress testing under the respective loads.
In the analogous art, Van Cleve teaches wherein the first maximum operating frequency and the second maximum operating frequency are determined as time-averaged operating frequencies or moving-averaged operating frequencies obtained over a duration of the stress testing under the respective loads (“the machine-readable storage medium includes instructions to determine core and un-core operating frequency variations… a base core operating frequency and a base un-core operating frequency for each one of the two or more processors.” par 0016 and “monitoring unit 110 stores an averaged value, e.g., a running average, of the data.” Par 0024 and “Monitoring unit 110 may perform a power burn test … monitoring unit 110 performs burn tests that makes the processor execute at the operating frequency limit allowed by the power consumption limit.” Par 0025 and “During the power burn test, monitoring unit 110 may engage each one of the processors 102A, 102B, 102C, 102D, and 102E, one by one, in exhaustive operations. During the exhaustive operations (stress tests), the respective registers of each processor is changed to indicate a change in the power consumption limit of the processor.” Par 0024) [the power burn tests measures and stores the running average of core and uncore (first and second frequencies) to identify performance variations].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr. and Van Cleve before him before the effective filing date of the claimed invention, to have modified Berry Jr. to incorporate the teachings of Van Cleve to have a running averaged frequency to ensure consistent and deterministic performance of the processor across various workloads. (Van Cleve, paragraph 41)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Berry Jr.
Regarding claim 11, Berry Jr. teaches a method comprising:
setting a target frequency of a central processing unit (CPU) (“The operating frequency of the processor is set in accordance with the validation start frequency (block 318). ” Par 0037 and Figure 3).
stress testing the CPU for the target frequency under a first load and a second load to determine a first maximum operating frequency of the CPU under the first load and a second maximum operating frequency of the CPU under the second load (“Each of the test workloads may be associated with distinct workload characteristics and may be designed to stress various components of the system at different levels, to stress the processor at different levels,” par 0028 and “beginning at the validation start frequency, the validation analysis unit 106 can increment the operating frequency of the processor 122 by 1% of the validation start frequency at each iteration… [and] can determine the highest frequency at which the processor 122 (when connected in the system 120) can operate before system failure. This highest operating frequency is herein referred to as “system maximum operating frequency.”” Par 0020), wherein the first load is lower than the second load (“Each of the test workloads may be associated with distinct workload characteristics and may be designed to stress various components of the system at different levels, to stress the processor at different levels,” par 0028);
determining whether a condition of the CPU has been reached based on detecting whether the first maximum operating frequency is lower than the target frequency by a margin due to thermal throttling (“A frequency guard band associated with the processor is the amount (or uncertainty margin) by which the operating frequency of the processor can deviate from the nominal operating frequency … [due to] changes in environmental conditions (e.g., ambient temperature), aging, system glitches, load and line variations, and other such transients can result in a deviation” Par 0003 and “in FIG. 3 to block 322 if it is determined that operating frequency of the processor is less than the target guard band frequency… If it is determined that system failure was detected, the flow continues at block 326.” Par 0040 and “The system maximum operating frequency is adjusted based on tester parametric data associated with the processor to yield the adjusted system maximum operating frequency (block 330)… the adjusted system maximum operating frequency can be calculated based…on knowledge of the voltage and temperature at the system maximum operating frequency determined at block 328” Par 0044 and Figure 3);
if the condition of the CPU has not been reached, increasing the target frequency of the CPU and repeating the stress testing and the determining for the increased target frequency (“The loop comprising the operations of blocks 320, 322, and 324 continues to execute until the operating frequency reaches the target guard band frequency or until system failure is detected.” Par 0041 and “If it is determined that the operating frequency of the processor is less than the target guard band frequency, the flow continues at block 322.” Par 0038 and “The operating frequency is incremented by a predetermined frequency factor” par 0041 and Figures 2-5); and
if the condition of the CPU has been reached, overclocking the CPU based on the first maximum operating frequency and the second maximum operating frequency (“The system parametric data (including the system maximum operating frequency) associated with the processor at the first workload and the first operating mode can be leveraged to determine the validation start frequency for validating the frequency guard bands associated with the processor at a second workload and/or a second operating mode.” Par 0036 and “The adjusted system maximum operating frequency is correlated with the tester maximum operating frequency (block 333)… if the adjusted system maximum operating frequency and the tester maximum operating frequency are equal (or differ by a predetermined value/percentage), the frequency guard bands associated with the processor are deemed to be validated” Par 0045 and par 20, 39 and 44) [the system enabled higher speeds (overclocking) by using the system maximum operating frequency and correlating it with the tester maximum frequency to determine a reliable performance limit].
Contingent Limitation
Claim 11 recites the following contingent limitations:
(a) if the condition of the CPU has not been reached, increasing the target frequency of the CPU and repeating the stress testing and the determining for the increased target frequency
(b) if the condition of the CPU has been reached, overclocking the CPU based on the first maximum operating frequency and the second maximum operating frequency
These limitations are contingent because they recite steps that are only required to be performed if their conditions are met. Limitation (a) only needs to be performed if the condition of the CPU has not been reached. Limitation (b) only needs to be performed if the condition of the CPU has been reached. These conditions are mutually exclusive, and therefore only one of limitations (a) and (b) can be performed. Therefore, the broadest reasonable interpretation (BRI) of claim 11 only requires only one of either limitation (a) or (b).
Regarding claim 14, Berry Jr. teaches the method of claim 11, further comprising: determining the first maximum operating frequency as a highest operating frequency of the CPU under the first load over increasing target frequencies of the CPU; and determining the second maximum operating frequency as a highest operating frequency of the CPU under the second load over the increasing target frequencies of the CPU (“The system parametric data (including the system maximum operating frequency) associated with the processor at the first workload and the first operating mode can be leveraged to determine the validation start frequency for validating the frequency guard bands associated with the processor at a second workload and/or a second operating mode” par 0036 and “The validation analysis unit 106 can increment (at regular intervals) the operating frequency of the processor 122 and can determine whether the increase in operating frequency resulted in system failure … the validation analysis unit 106 can determine the highest frequency at which the processor 122 (when connected in the system 120) can operate before system failure. This highest operating frequency is herein referred to as “system maximum operating frequency.”” par 0020).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see pages 3, filed 06/26/2026, with respect to the rejection(s) of claim 6 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Berry Jr. in view of Yan. Yan describes an iterative process that identifies failures based on thermal limits and implements the highest stable frequency found across different test loads. Examiner respectfully points to the updated mapping of claim 6.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Chabukswar et al. (US 2018/0314289 A1) teaches a throttling circuit that detects execution of instructions at a first frequency level, increments a cycle counter to count the number of cycles a processing engine is paused and in response to the cycle counter reaching a threshold, changing the operating frequency to a second frequency level.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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