DETAILED ACTION
Claims 1-15 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 09/27/2024 for application number 18/851,838.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: Claim 11, 4th paragraph reads “increasing the target frequency of the CPU and repeating the stress testing and determining; and” (emphasis added). The last part of the limitation after “determining” is incomplete. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Berry Jr. et al. (US 2015/0057975 A1).
Regarding claim 1, Berry Jr. teaches a non-transitory machine-readable medium comprising instructions that, when executed by a processor (Figures 1 and 6), cause the processor to:
set a target frequency of a central processing unit (CPU) (“the target guard band frequency, the nominal operating frequency, and/or the nominal operating voltage that corresponds to the selected workload and the selected operating mode can also be determined.” Par 0029 and “the target guard band frequency can be the upper limit on the frequency guard bands associated with the processor.” Par 0038 and Figure 2);
benchmark the CPU under a first load and a second load, wherein the first load is lighter than the second load (“Each of the test workloads may be associated with distinct workload characteristics and may be designed to stress various components of the system at different levels, to stress the processor at different levels, to test the interactions between the processor and the components of the system, etc.” par 0028 and “The system parametric data … associated with the processor at the first workload … can be leveraged to determine the validation start frequency for validating the frequency guard bands associated with the processor at a second workload and/or a second operating mode” par 0036 and Figure 2) [the workloads stress test the processor at different levels, which encompasses using a first load that is lighter (lower stress level) than a second load to determine validation parameters];
determine a first operating frequency of the first load and second operating frequency of the second load (“The system parametric data (including the system maximum operating frequency) associated with the processor at the first workload and the first operating mode can be leveraged to determine the validation start frequency for validating the frequency guard bands associated with the processor at a second workload and/or a second operating mode.” Par 0036) [the process determines the operating frequency (maximum) for a first load and uses that data to determine a corresponding operating frequency for the second load]; and
if the first operating frequency is lower than the target frequency by a margin and a CPU thermal condition had been met, then store the first operating frequency and the second operating frequency for continued operation of the CPU, otherwise repeat the benchmark and redetermine the first operating frequency and the second operating frequency until the first operating frequency is lower than the target frequency by the margin and the CPU thermal condition is met (“If it is determined that the processor in the system test environment should be validated in accordance with another workload, the flow loops back to block 204 in FIG. 2, where the next workload is identified and loaded into memory associated with the processor for execution by the processor.” Par 0047 and “The loop comprising the operations of blocks 320, 322, and 324 continues to execute until the operating frequency reaches the target guard band frequency or until system failure is detected.” Par 0041 and “the validation analysis unit 106 can also determine the system parametric data including the … temperature generated by the processor 122 at the system maximum operating frequency. The validation analysis unit 106 can store an indication of the system maximum operating frequency and the system parametric data” par 0020 and paragraphs 3, 42-47 and Figures 2-5) [the validation loop evaluates if operating frequencies satisfy a target band uncertainty margin and thermal conditions; these parameters are stored once criteria are met; if not, the redetermination process is repeated].
Regarding claim 2, Berry Jr. teaches the non-transitory machine-readable medium of claim 1, wherein the instructions are to:
determine the first operating frequency as a first maximum frequency from the benchmark under the first load (“The highest frequency at which the processor can operate in the system test environment before system failure can be designated as the system maximum operating frequency associated with the processor.” Par 0042 and paragraph 36) [the last stable frequency is designated as the system maximum operating frequency]; and
determine the second operating frequency as a second maximum frequency from the benchmark under the second load (“The validation analysis unit 106 can then execute operations described above at stage D and stage E to determine the actual system maximum operating frequency associated with the processor 122” par 0023 and “ If it is determined that the processor in the system test environment should be validated in accordance with another workload, the flow loops back to block 204 in FIG. 2,” par 0047 and paragraph 36).
Regarding claim 3, Berry Jr. teaches the non-transitory machine-readable medium of claim 2, wherein:
the first maximum frequency is a maximum over a set of target frequencies of the CPU used in the benchmark (“Starting at the nominal operating frequency, the existing frequency guard banding procedures either execute a binary search algorithm or sequentially increment the operating frequency of the processor to determine the maximum operating frequency before which system failure is detected” par 0011); and
the second maximum frequency is a maximum over the set of target frequencies of the CPU used in the benchmark (“The validation analysis unit 106 can then execute operations described above at stage D and stage E to determine the actual system maximum operating frequency associated with the processor 122” par 0022 and Figure 1) [the benchmarking operations are repeated for a second load to determine its specific maximum stable frequency over the set of frequencies tested in that iteration].
Regarding claim 5, Berry Jr. teaches the non-transitory machine-readable medium of claim 1, wherein the margin is between 10% and 20% (“if a frequency guard band that is 15% higher than the nominal operating frequency is desired, the validation analysis unit 106 may halt the frequency guard band validation process when the operating frequency is at least 15% higher than the nominal operating frequency.” Par 0024).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. in view of Branover et al. (US 2013/0246820 A1).
Regarding claim 4, Berry Jr. teaches the non-transitory machine-readable medium of claim 1. However, Berry Jr. does not explicitly teach wherein the CPU thermal condition comprises: a CPU temperature exceeding a threshold temperature; or a thermal throttling of the CPU exceeding a threshold thermal throttling.
In the analogous art, Branover teaches wherein the CPU thermal condition comprises:
a CPU temperature exceeding a threshold temperature; or a thermal throttling of the CPU exceeding a threshold thermal throttling (“The control logic within the power management unit 20 may throttle a given processing node in response to detecting a temperature reading from a sensor near or within the given processing node exceeds a respective threshold.” Par 0100 and “Responsive to determining a count of throttling exceeds a first threshold within a time interval for the given processing node, the control logic within the power management unit 20 may reduce the power limit for the given processing node.” Par 0101) [the control loop reacts both to a specific temperature threshold being exceeded and to the monitored amount of thermal throttling exceeding a limit].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr. and Branover before him before the effective filing date of the claimed invention, to have modified Berry Jr. to incorporate the teachings of Branover to consider the CPU temperature exceeding a threshold or a thermal throttling exceeding a threshold thermal throttling to increase processor utilization while preventing CPU overheating. (Branover, paragraph 6)
Claims 6, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. in view of Han (US 2021/0365269 A1).
Regarding claim 6, Berry Jr. teaches a device comprising:
a central processing unit (CPU) (Figure 1, processor 122);
storage connected to the CPU (Figure 6, memory unit 606 and paragraph 15), the storage including executable instructions to:
iterate over a series of increasing clock frequencies for the CPU (“The validation analysis unit 106 can increment (at regular intervals) the operating frequency of the processor 122 … For example, beginning at the validation start frequency, the validation analysis unit 106 can increment the operating frequency of the processor 122 by 1% of the validation start frequency at each iteration.” Par 0020);
initiate execution of different test loads by the CPU (“block 204 in FIG. 2, where the next workload is identified and loaded into memory associated with the processor for execution by the processor.” Par 0047) and store a maximum frequency of the CPU for each test load of the different test loads (“The validation analysis unit 106 can store an indication of the system maximum operating frequency … in the system parametric data store 108.” Par 0020);
determine that a condition of the CPU has been reached based on the maximum frequency of a test load of the different test loads (“the validation analysis unit 106 may halt the frequency guard band validation procedure … when the operating frequency of the processor 122 equals or exceeds the target guard band frequency” par 0024 and “The loop comprising the operations of blocks 320, 322, and 324 continues to execute until the operating frequency reaches the target guard band frequency” par 0041) [a condition is considered reached once the processor achieves a specific frequency threshold (target maximum) during execution of a test load; the processor’s state is continuously evaluated]; and
when the condition of the CPU has been reached, cease iteration over the series of increasing clock frequencies (“the validation analysis unit 106 may halt the frequency guard band validation procedure … when the operating frequency of the processor 122 equals or exceeds the target guard band frequency” par 0024).
However, Berry Jr. does not explicitly teach overclock the CPU based on the maximum frequency of the CPU for each test load.
In the analogous art, Han teaches overclock the CPU based on the maximum frequency of the CPU for each test load (“Moreover, Step 5 (S50) performing, by the heavy load testing module 14, a heavy load testing on the multi-core CPU; and the heavy load testing module 14 performs a heavy load test on the multi-core CPU 11 with the starting clock rate and the operating voltage defined by the overclocking operating parameters,” par 0050 and “a BIOS unit can automatically evaluate a thermal dissipation environment of a multi-core CPU and offer the optimized proposals for overclocking.” Par 0052 and “the clock rate (frequency) of 4900 MHz is deemed as appropriate for over-clocking on the CPU … Then, the user can make his decision on whether overclocking results are to be saved or not.” Par 0058 and paragraphs 54-57 and Figure 1) [the system evaluates the CPU’s environment to determine and propose the best speed for overclocking; it identifies a specific frequency reached during heavy load testing and using that value as a basis for the overclocked setting].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr. and Han before him before the effective filing date of the claimed invention, to have modified Berry Jr. to incorporate the teachings of Han to overclock the CPU based on the maximum frequency to ensure quick process completion without causing system shutdowns. (Han, paragraph 22)
Regarding claim 7, Berry Jr. and Han teach the device of claim 6. Berry Jr. further teaches wherein the instructions are to detect that the maximum frequency of a lowest test load of the different test loads is below a threshold frequency to determine that the condition of the CPU has been reached (“the workload can be selected from a plurality of test workloads… designed to stress various components of the system at different levels, to stress the processor at different levels, ” Par 0028 and “The loop comprising the operations of blocks 320, 322, and 324 continues to execute until the operating frequency reaches the target guard band frequency” par 0041 and Figure 2) [this describes an iterative process using workloads of varying intensity where the system detects if a processor fails to reach a target frequency threshold, determining the processor’s maximum stable condition].
Regarding claim 10, Berry Jr. and Han teach the device of claim 6. Han further teaches wherein the instructions are to increase CPU voltage when increasing a clock frequency for the CPU (“The adjustment module 13 performs adjustment of the clock rate and the voltage of the multi-core CPU 11” par 0049 and “the adjustment module 13 retrieves other overclocking operating parameters to adjust the working clock rate and the working voltage,” par 0052) [the automated module applies specific voltage increases corresponding to higher clock rates from a database].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Berry Jr. in view of Han and in further view of Branover.
Regarding claim 9, Berry Jr. and Han teach the device of claim 7. However, Berry Jr. and Han do not explicitly teach wherein the instructions are to: detect a CPU temperature exceeding a threshold temperature, or detect thermal throttling of the CPU exceeding a threshold thermal throttling, so as to determine that the condition of the CPU has been reached.
In the analogous art, Branover teaches wherein the instructions are to:
detect a CPU temperature exceeding a threshold temperature, or detect thermal throttling of the CPU exceeding a threshold thermal throttling, so as to determine that the condition of the CPU has been reached (“The control logic within the power management unit 20 may throttle a given processing node in response to detecting a temperature reading from a sensor near or within the given processing node exceeds a respective threshold.” Par 0100 and “Responsive to determining a count of throttling exceeds a first threshold within a time interval for the given processing node, the control logic within the power management unit 20 may reduce the power limit for the given processing node.” Par 0101) [the system monitors temperatures and throttling counts against thresholds to determine when the processor’s operational limit (condition) is reached].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Berry Jr., Han and Branover before him before the effective filing date of the claimed invention, to have modified Berry Jr. and Han to incorporate the teachings of Branover to consider the CPU temperature exceeding a threshold or a thermal throttling exceeding a threshold thermal throttling to increase processor utilization while preventing CPU overheating. (Branover, paragraph 6)
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Van Cleve et al. (US 2020/0159303 A1) in view of Han.
Regarding claim 11, Van Cleve teaches a method comprising:
setting a target frequency of a central processing unit (CPU) (“the average of the operating frequencies that may be called a target operating frequency is below a first group of operating frequencies and is above a second group of operating frequencies.” Par 0013 and Figure 1);
stress testing the CPU under a first load and a second load, wherein the first load is lower than the second load, to determine a first maximum frequency of the first load and second maximum frequency of the second load (“the processors may be put under test and each one of the processors may perform a burn test that makes the processor execute at the operating frequency limit allowed by the power consumption limit… the power consumption limit is modified step-by-step and the operating frequency is measured.” Par 0013 and “The variations may be obtained by varying the power consumption limit in a plurality of steps and measuring the un-core operating frequency at each step” par 0032) [the loads correspond to power consumption limits that are modified in discrete steps during burn (stress) tests to measure maximum operating frequency supported at each power level].
However, Van Cleve does not explicitly teach determining whether a condition of the CPU has been reached based on the first maximum frequency of the first load; if the condition of the CPU has not been reached, increasing the target frequency of the CPU and repeating the stress testing and determining; and if the condition of the CPU has been reached, overclocking the CPU based on the first maximum frequency and the second maximum frequency.
In the analogous art, Han teaches determining whether a condition of the CPU has been reached based on the first maximum frequency of the first load (“determining whether the working clock rate of the multi-core CPU approaches the maximum clock rate or not,” par 0011 and “a determination whether the working results data such as the working clock rate … have exceeded the starting clock rate or ending clock rate … of the multi-core CPU 11 is made.” Par 0036) [the measured clock rate is used to determine whether the CPU has reached specific conditions, such as approaching maximum clock rate or predefined threshold limits];
if the condition of the CPU has not been reached, increasing the target frequency of the CPU and repeating the stress testing and determining (“(2b) if the working clock rate of the multi-core CPU does not approach the maximum clock rate, repeatedly conducting Heavy Load Testing (HLT) of Step 4 by using new clock rate which is more than the starting clocking rate … and then repeatedly conducting Steps 5 and 6 to acquire a clock rate that is deemed suitable to the computer device.” Par 0039 and “If not beyond the limits, the adjustment module 13 retrieves other overclocking operating parameters to adjust the working clock rate and the working voltage,” par 0052); and
if the condition of the CPU has been reached, overclocking the CPU based on the first maximum frequency and the second maximum frequency (“(2a) if the working clock rate of the multi-core CPU approaches the maximum clock rate, then stopping the Heavy Load Testing (HLT) and the computer device is deemed as it could be enhanced by overclocking under the maximum clock rate;” par 0021 and “ the clock rate (frequency) of 4900 MHz is deemed as appropriate for overclocking on the CPU of model number i9-10900K. Then, the user can make his decision on whether overclocking results are to be saved or not. For example, “Do you want to save CPU 2 core for 5300 all core for 4800 MHz setting and reset”” par 0058) [this shows an iterative process where the clock frequency is increased and stress tested (HLT) until a maximum limit is approached, at which point the final stable overclocking parameters are saved].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Van Cleve and Han before him before the effective filing date of the claimed invention, to have modified Van Cleve to incorporate the teachings of Han to overclock the CPU based on the first maximum frequency to ensure quick process completion without causing system shutdowns. (Han, paragraph 22)
Regarding claim 12, Van Cleve and Han teach the method of claim 11. Han further teaches wherein determining whether the condition of the CPU has been reached further includes determining the CPU to be at an elevated thermal state (“Step 5 (S50): determining whether the working voltage and the working temperature of the multi-core CPU exceeds the voltage upper limit and the temperature upper limit or not.” Par 0035 and paragraph 11) [the method determines if a CPU is at an elevated thermal state if the temperature exceeds the temperature upper limit].
Regarding claim 13, Van Cleve and Han teach the method of claim 11. Han further teaches further comprising, when increasing the target frequency of the CPU, increasing a voltage of the CPU if below a safe operating voltage for the target frequency (“the adjustment module 13 retrieves other overclocking operating parameters to adjust the working clock rate and the working voltage” par 0052 and “the overclocking operating parameters include safe overclocking operating parameters and stable overclocking operating parameters… respective overclocking operating parameters define working clock rate and working voltage thereof.” Par 0028).
Regarding claim 14, Van Cleve and Han teach the method of claim 11. Van Cleve further teaches further comprising:
determining the first maximum frequency as a highest frequency of the first load over increasing target frequencies of the CPU (“The variations may be obtained by varying the power consumption limit in a plurality of steps and measuring the core and un-core operating frequency at each step to generate the core and un-core operating frequency variations.” Par 0028); and
determining the second maximum frequency as a highest frequency of the second load over the increasing target frequencies of the CPU (“while gradually modifying the power consumption limit of the processor, monitoring unit 110 performs burn tests that makes the processor execute at the operating frequency limit allowed by the power consumption limit.” Par 0025) [varying power limits (loads) across discrete steps measure maximum core/uncore operating frequency limit at each level; establishing highest supported frequency for each specific load].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Van Cleve in view of Han and in further view of Branover.
Regarding claim 15, Van Cleve and Han teach the method of claim 11. However, Van Cleve and Han do not explicitly teach further comprising activating different processing cores of the CPU to establish the first load and the second load.
In the analogous art, Branover teaches activating different processing cores of the CPU to establish the first load and the second load (“if all four processing nodes 11 are active and processing a workload, their respective local power limits may be set to equal values. However, if two processing nodes 11 are active while the other two are in an idle state, the local power limits for the active nodes may be increased with the local power limits for the idle nodes may be decreased correspondingly.” Par 0038 and Figure 1) [this shows establishing different loads by varying number of active cores].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Van Cleve, Han and Branover before him before the effective filing date of the claimed invention, to have modified Van Cleve and Han to incorporate the teachings of Branover to reallocate power and thermal budgets from idle cores to active ones to enable higher performance and overclocking boosts while maintain the system within its global power limit. (Branover, paragraph 38)
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Yan et al. (US 2022/0113757 A1) teaches execution of an optimization model to select values for overclocking parameters for a processor, performance of benchmark testing, assigning a score associated with benchmark testing and selecting the values to overclock based on the score comparison.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176