Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-3, 5-17, 19-21, and 31-42 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7-21, 31-37 and 41-42 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Khan et al. (US 20190146717 A1).
Regarding claim 1: Khan discloses a compute device for efficiently accessing memory data (FIG. 1) comprising: an array of memory cells (FIG. 6); a memory access logic (media access circuitry 108 and 118, FIG. 1) programmable to generate a write allocation (write operation on row or column of array, FIG. 4) that maps an input comprising elements of data in a first sequence (row or column of array, FIG. 6) to the memory cells of the array and a read allocation sequence (read operation on row or column, FIG. 5) that maps the memory cells of the array to an output comprising elements of data in a second sequence (row or column of array, FIG. 6); and a memory controller (controllers 106 and 116, FIG. 1) arranged to write the elements of data at the input to the array based on the write allocation (write operation, FIG. 4) and to read the elements of data stored in the array to the output based on the read allocation (read operation, FIG. 5).
Regarding claim 2: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the first sequence is different to the second sequence such that a first sequence order (e.g. selected column of FIG. 6) of the elements of data at the input is different to a second sequence order of the elements of data at the output (output is from all rows, FIG. 6).
Regarding claim 3: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the input is a parallel input of a first width (input selected column number of data bits, FIG. 6) and the output is a parallel output of a second width (output row number of bits, FIG. 6), wherein the first and second widths are the same (array of FIG. 6 can be expanded to be square for equal width of data for both rows and columns).
Regarding claim 5: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the elements of data at the input and output are one of: single bits of a data word (single bits of data of array, FIG. 6) or multi-bit words of a data string (multiple-bit possible in typical memory devices, par. 19).
Regarding claim 7: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the write allocation maps the input to respective first subsets of the memory cells of the array in a first subset order (write operation can be on subset of input row or column of matrix, FIG. 6), and the read allocation reads respective second subsets of the memory cells to the output in a second subset order (read operation can be on subset of output column or row, FIG. 6).
Regarding claim 8: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the first subsets each comprise a respective first arrangement of memory cells of the array and the second subsets each comprise a respective second arrangement of memory cells of the array (subsets can be further divided of the array, FIG. 6).
Regarding claim 9: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein each of the respective first arrangements are different to each of the respective second arrangements (different arrangements possible from given memory array cells, FIG. 6).
Regarding claim 10: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the first arrangements each have a width equal to a first width of the input and a second width of the output (width of input row or column, width of output column or row, FIG. 6).
Regarding claim 11: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the first and second arrangements each have a width equal to a first width of the input and a second width of the output (the different arrangements of memory cells able to have their own width values, FIG. 6).
Regarding claim 12: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the first subset order is different to the second subset order (subsets of arrays can be different, FIG. 6).
Regarding claim 13: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein each of the first subsets comprises a row or a column of the memory cells of the array (subset can be a row or column of array, FIG. 6).
Regarding claim 14: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein each of the second subsets comprises a row or a column of the memory cells of the array (subset can be a row or column of array, FIG. 6).
Regarding claim 15: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein each of the first subsets of the memory cells of the array are adjacent such that the input is mapped to respective first subsets of adjacent memory cells of the array (write operation on particular rows and/or columns of array, par. 25, FIG. 4 and 6), and each of the second subsets of the memory cells of the array are adjacent such that the output is read from respective second subsets of adjacent memory cells of the array (read operation on particular rows and/or columns of array, par. 25, FIG. 4 and 6).
Regarding claim 16: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the elements of data at the input and output are one of single bits of a data word (individual bits, par. 19, FIG. 6) or multi-bit words of a data string (multiple-bit possible in typical memory devices, par. 19), and wherein each single bit or multi-bit word is mapped to respective first subsets of adjacent memory cells of the array (particular columns and rows can be selected for write, par. 25, FIG. 6) , and each single bit or multi-bit word is read to the output from respective second subsets of adjacent memory cells of the array (particular columns and rows can be selected for read, par. 25, FIG. 6).
Regarding claim 17: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the second subset order of the memory cells of the array read to the output is a predetermined shift (rearrangement of tiles of data matrix, FIG. 8-11) of the first subset order of the memory cells of the array.
Regarding claim 19: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the first subset order is a butterfly transposition (transposition of tiles of data matrix, FIG. 8-11) of the elements of data at the input.
Regarding claim 20: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein each respective first subset of the memory cells of the array and each respective second subset of the memory cells of the array (particular rows and/or columns of matrix, par. 25) both comprise at least one single bit from each data word (individual bits, par. 19, FIG. 6) or at least one multi-bit word from each data string at the input (multiple-bit in typical memory devices, par. 19).
Regarding claim 21: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein each of the first subsets comprises a row or a column of the memory cells of the
array (subset can be a row or column of array of data matrix, FIG. 6), wherein each row or column of the memory cells of the array of the first subset comprises a plurality of multi-bit words of one data string (subset of data matrix possible to have multiple-bit in typical memory device, par. 19) of a plurality of data strings at the input, and wherein each respective second subset of the memory cells of the array comprises at least one multi-bit word from each data string (subset of data matrix possible to have multiple-bit in typical memory device, par. 19) of the plurality of data strings at the input.
Regarding claim 31: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the memory cells of the array are divided into a first memory cell subgroup and a second memory cell subgroup; the input comprises a first input frame and a second input frame (input of particular rows and/or columns, in this case the desired subset can be a small size to match the frame, par. 25, FIG. 6); the first input frame comprises a first data element and second data element (given frame can include certain data from data matrix, FIG. 6); the second input frame comprises a third data element and a fourth data element (given frame can include certain data from data matrix, FIG. 6); and the write allocation maps: the first data element to a first memory cell in the first memory cell subgroup (write operation accounts for writing data into target block of cells of the memory media, where the specific allocation mapping is possible accounting for the next limitations regarding other data elements, par. 26); the second data element to first memory cell in the second memory cell subgroup; the third data element to a second memory cell of the first memory cell subgroup; and the fourth data element to a second memory cell of the second memory cell subgroup.
Regarding claim 32: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein a transformational relationship between the location of the first memory cell and second memory cell in the first memory cell subgroup corresponds to or is identical to a transformational relationship between the location of the first memory cell and second memory cell in the second memory cell subgroup (bit manipulation operation of data can be performed on different subgroups of the data matrix and yield similar results, par. 26).
Regarding claim 33: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the transformational relationship is a translational or a rotational relationship (rotation manipulation of data, par. 26-27) , wherein the transformational relationship is to rotate or translate by a single memory cell from one memory cell to an adjacent memory cell (manipulation can be modified to specific limitations, it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art).
Regarding claim 34: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein an order of the first data element in the first input frame corresponds with an order of the third data element in the second input frame, and an order of the second data element in the first input frame corresponds with an order of the fourth data element in the second input frame (data of the data matrix among sequences of rows and columns decided, FIG. 6; it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art)
Regarding claim 35: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the read allocation maps the memory cells of the array to an output comprising a first output frame comprising the first data element and the third data element and a second output frame comprising the second data element and the fourth data element (read operation on particular rows and/or columns of array, par. 25, FIG. 4 and 6; the specific mapping as described would be obvious since it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art).
Regarding claim 36: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein an order of the first data element in the first output frame corresponds with an order of the second data element in the second output frame (sequence order of the chosen particular rows and/or columns of the frame can be chosen, par. 25, FIG. 6; the order would be obvious since it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art).
Regarding claim 37: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein an order of the third data element in the first output frame corresponds with an order of the fourth data element in the second output frame (sequence order of the chosen particular rows and/or columns of the frame can be chosen, par. 25, FIG. 6; the order would be obvious since it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art).
Regarding claim 41: Khan discloses a compute device for efficiently accessing memory data (FIG. 1), wherein the first data element (buffer memory 13 coupled to detector array 6, FIG. 3) corresponds to a first detected intensity (detector array element 6 detects light energy, FIG. 3) at a first port in an array of ports at an output plane (detector array element 6 detects light energy, FIG. 3)of an optical Fourier transform stage (Fourier transform lens 3 and 5, FIG. 3) and the third data element (buffer memory 13 coupled to detector array 6, FIG. 3) corresponds to a second detected intensity (detector array element 6 detects light energy, FIG. 3) at the first port, and wherein the second data element corresponds to a third detected intensity at a second port in the array of ports and the fourth data element corresponds to a fourth detected intensity at the second port (data elements to corresponding detected intensities found through buffer memory 12 coupled to detector array 6, FIG. 13).
Regarding claim 42: Khan discloses a method for a compute device for efficiently accessing memory data (FIG. 1), generating, in a memory access logic (media access circuitry 118), a write allocation (write operation on row or column of array, FIG. 4) that maps an input to memory cells of an array of memory cell (FIG. 6) in a first sequence (row or column of array, FIG. 6) and a read allocation (read operation on row or column, FIG. 5) that maps the memory cells of the array to an output in a second sequence (row or column of array, FIG. 6); writing elements of data at the input to the array (write operation, FIG. 4) based on the write allocation; and reading elements of data stored in the array (read operation, FIG. 5) to the output based on the read allocation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Khan et al. (US 20190146717 A1) in view of Ishii et al (US 20190050328 A1).
Regarding claim 6: Khan does not disclose a memory, wherein the most significant to least significant bit or word of each single bit or multi-bit word is mapped to the input or read to the output in parallel.
Ishii does disclose a memory control apparatus (100, FIG. 1), wherein the most significant to least significant bit or word of each single bit or multi-bit word is mapped to the input or read to the output in parallel (pixels of the data stored into words of the memory going through the bits, par. 128-38, FIG. 32-40).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Khan with the configuration of Ishii to have the specific pattern or order for mapping can be applied to the data matrix.
Claim(s) 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Khan et al. (US 20190146717 A1) in view of Stoll et al (US5497253A).
Regarding claim 38: Khan does not disclose a memory device, wherein the first input frame and second input frame each include data corresponding to detected light intensity values at an output plane of an optical Fourier transform stage.
Stoll does disclose a neural network where (FIG. 3), wherein the first input frame and second input frame each include data corresponding to detected light intensity values (buffer memory 13 coupled to detector array 6, FIG. 3) at an output plane (array disposed along a correlation plane, FIG. 3) of an optical Fourier transform stage (Fourier transform lens 3 and 5, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Khan with the memory configuration of Stoll to allow the system to couple the data of the memory with the described light detector and Fourier transform stage as the claim.
Regarding claim 39: Khan does not disclose a memory device, wherein each of the first and second data elements corresponds to a detected light intensity value at a port in an array of ports at an output plane of an optical Fourier transform stage, and wherein each of the third and fourth data elements corresponds to a detected light intensity value at a port in an array of ports at an output plane of the same or another optical Fourier transform stage.
Stoll does disclose a neural network where (FIG. 3), wherein each of the first and second data elements (buffer memory 13 coupled to detector array 6, FIG. 3) corresponds to a detected light intensity value (detector array element 6 detects light energy, FIG. 3) at a port in an array of ports at an output plane (array disposed along a correlation plane, FIG. 3) of an optical Fourier transform stage (Fourier transform lens 3 and 5, FIG. 3), and wherein each of the third and fourth data elements corresponds to a detected light intensity value at a port in an array of ports at an output plane of the same or another optical Fourier transform stage (buffer memory can include additional data elements and connected to the same Fourier transform lens. FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Khan with the memory configuration of Stoll to allow the system to couple the data of the memory with the described light detector and Fourier transform stage as the claim.
Regarding claim 40: Khan does not disclose a memory device, wherein a relative order of the first and second data elements in the first input frame and a relative order of the third and fourth data elements in the second input frame each correspond to a relative position of ports in an array of ports at an output plane in the respective optical Fourier transformation stage, wherein the relative order is adjacent or subsequent positions in an order and the relative position is an adjacent position in the array of ports.
Stoll does disclose a neural network where (FIG. 3), wherein a relative order of the first and second data elements in the first input frame and a relative order of the third and fourth data elements in the second input frame each correspond to a relative position of ports in an array of ports at an output plane in the respective optical Fourier transformation stage, wherein the relative order is adjacent or subsequent positions in an order and the relative position is an adjacent position in the array of ports (I would be obvious to have the chosen order of the data matric elements to be as described, since it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the ar.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHONY THINH TANG/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights