Prosecution Insights
Last updated: October 04, 2026
Application No. 18/852,454

Logic device and logic computation architecture

Final Rejection §102
Filed
Apr 05, 2025
Priority
Mar 30, 2022 — FR FR2202874 +1 more
Examiner
CRAWFORD, JASON
Art Unit
Tech Center
Assignee
Université Grenoble Alpes
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
936 granted / 1101 resolved
+25.0% vs TC avg
Moderate +9% lift
Without
With
+9.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
20 currently pending
Career history
1114
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
40.2%
+0.2% vs TC avg
§102
44.2%
+4.2% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1101 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-8, 10 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2019/0386662). In regards to claim 1, Lin discloses of a logic device comprising: a first arm (for example 201) extending along a first direction and letting a charging current flow therethrough, a second arm (for example 207) extending along the first direction and letting a charging current flow therethrough, a channel (for example 205) connecting said first arm (201) to said second arm (207, see Fig 3), the channel (205) being along a second direction perpendicular to the first direction (see Figs 3-4), the channel including three zones, namely: a first zone of contact with said first arm (201), a second zone of contact with said second arm (207); and a central zone connecting said two zones of contact (see Figs 3-4), said first arm (201), said second arm (207) and the channel (205) performing a first conversion in said first zone of contact and a second conversion in said second zone of contact, the first conversion being conversion of a charging current flowing through said first arm (201), into a spin current flowing through the channel (205), and the second conversion being conversion of a spin current flowing through the channel (205), into a charging current flowing through said second arm (207), and a control unit (for example see transistors above 201 and 207) for controlling the direction of the charging current flowing in said second arm, the control unit comprising at least one electrical control sub-unit of one of the two conversions (for example see Figs 3-4). In regards to claim 2, Lin discloses of the logic device according to claim 1, wherein a control sub-unit of said at least one electrical control sub-unit comprises a control sub-unit of the first conversion and controls the direction of the charging current flowing through said second arm (201) by controlling the direction of the spin current spins by an electrical control of the first conversion (see Figs 3-4). In regards to claim 3, Lin discloses of the logic device of claim 2, wherein said control sub-unit for the first conversion includes a voltage source (for example see 0V, Vdd and -Vdd) and an electrical contact, the electrical contact being in contact with said first contact zone (see Figs 3-4), the voltage source controlling the potential of the electrical contact (see Figs 3-4). In regards to claim 4, Lin discloses of the logic device according to claim 1, wherein a control sub-unit of said at least one electrical control sub-unit comprises a control sub-unit of the second conversion and is adapted to control the direction of the charging current by an electrical control of the second conversion (see Figs 3-4). In regards to claim 5, Lin discloses of the logic device according to claim 4, wherein said control sub-unit for the second conversion comprises a voltage source and an electrical contact, the electrical contact being in contact with said second contact zone, the voltage source controlling the potential of the electrical contact (see Figs 3-4). In regards to claim 6, Lin discloses of the logic device according to claim 3, wherein the electrical contact comprises a multilayer (for example see Figs 2A, 3-4, 6, 8A) formed at least by an insulating layer and a metal layer, the insulating layer resting on said arms (201, 207) and said channel (205, see Figs 2A, 3-4, 6, 8A). In regards to claim 7, Lin discloses of the logic device according to claim 3, wherein the electrical contact rests on a portion of channel (205) and on a portion of said arm (201, 207, see Figs 3-4). In regards to claim 8, Lin discloses of the logic device to claim 1, wherein said arms (201, 207) and said channel (205) form an H (for example see Figs 3-8A). In regards to claim 10, Lin discloses of the logic device according to claim 1, wherein said arms (201, 207) are made of a first material, said contact zones are made of a second material and said channel (205) are made of a third material distinct from said first material and from said second material (for example see Paragraphs 0055-0060). In regards to claim 12, Lin discloses of the logic device according to claim 1, wherein the logic device performs a logic operation on two logic inputs to obtain a logic output, the state of the logic output being the direction of the current circulating in said second arm (207), the logic state of a first input is the value of a potential applied to a control sub-unit and the logic state of a second input is the direction of the current circulating in said first arm, or the logic state of a first input is the value of a current applied to a control sub-unit and the logic state of a second input is the value of another current applied to a control sub-unit, or the logic state of a first input is the value of the potential applied to the control sub-unit of the first conversion and the logic state of a second input being the value of the potential applied to the control sub-unit of the second conversion (see Figs 2A-8A). In regards to claim 13, Lin discloses of a logic computation architecture including at least two logic devices according to claim 1, the logic computation architecture satisfying at least one of the following properties: the first arm (201) of one of said two logic devices is coincident with the second arm (207) of the other logic device, and the second arm (207) of one of said two logic devices is connected with an electrical control sub-unit of one of the two conversions (see Figs 2A-8A). Allowable Subject Matter Claims 9, 11 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: In regards to claim 9, the prior art does not disclose of the logic device according to claim 1, wherein said arms and said channel are made of the same material, nor would it have been obvious to one of ordinary skill in the art to do so. Claims 11 and 16 are also objected to as being dependent on claim 9. In regards to claim 14, the prior art does not disclose of wherein said channel is made of a ferroelectric material, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 15 is also objected to as being dependent on claim 15. Response to Arguments Applicant's arguments filed 8/21/2026 have been fully considered but they are not persuasive. The Applicant argues the Lin prior art only discloses of utilizing a single type of conversion of inverse Rashba-Edelstein effect (i.e. spin-to-charge conversion) instead of the claimed first and second conversion, which also includes charge-to-spin conversion (Rashba-Edelstein effect); however, the Examiner respectfully disagrees. As can be seen within example paragraphs 0021, 0023, 0064 and Table 1, the prior art discloses of the combination of both conversion examples (charge-to-spin and spin-to-charge) and dynamics as claimed where the electrodes carry the charge currents. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hong et al. (US 2020/0365652) Manipatruni et al. (US 2020/0211608) Manipatruni et. Al. (US 2019/0325932) Manipatruni et al. (US 2017/0243917) THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Thurs 6:30am-3:00pm, Fri 6:30am-12:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON M CRAWFORD/Primary Examiner, Art Unit 2845
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Prosecution Timeline

Apr 05, 2025
Application Filed
Apr 02, 2025
Response after Non-Final Action
May 22, 2026
Non-Final Rejection mailed — §102
Aug 21, 2026
Response Filed
Sep 21, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+9.1%)
1y 10m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1101 resolved cases by this examiner. Grant probability derived from career allowance rate.

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