DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
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Applicant's arguments filed 07/21/2026 have been fully considered but they are not persuasive. Applicant alleges that Negishi does not teach or suggest the conductive path disposed along a second plane that is parallel to the first plane, wherein a first portion of the conductive path is configured to be straight and parallel to the contacting system, where the first portion extends along a first direction between the needle probe card and the closing terminal, however the applicant is respectfully reminded that, while it might be evident, by comparing the patented structure of Negishi with the instant specification and drawings, that the claimed invention is different from the Prior Art made of record, that is not the test for patentability. Rather, it is the language of the claims what defines the meets and bounds of the instant invention. In this case, Negishi teaches a portion of the conductive path (short arrow) disposed along a second plane and parallel to the first plane (long arrow), wherein a first portion of the conductive path (short arrow) is configured to be straight and parallel to the contacting system, where the first portion extends along a first direction between the needle probe card and the closing terminal.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 9-10, 15-16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Negishi et al. (US 2015/0241472).
Regarding claim 1-3, 5-7 and 9-10, Negishi teaches a test system comprising:
a contacting system (200) configured to hold and be electrically connected to a wafer (Fig. 2, item 40) that includes a plurality of power semiconductor devices, the contacting system including a closing contact conductive portion (220) with a first surface that shares a first plane with a surface of the wafer (Fig. 2);
a test machine (60) configured to execute, on a first power semiconductor device among the plurality of power semiconductor devices, a test comprising high-voltage or a high-current test function (para. 2), the test machine including:
a needle probe card (104) including at least a first needle configured to contact the first power semiconductor device during the test;
a closing terminal (120) that is disposed along a first direction at a first distance from the needle probe card, the closing terminal being configured to contact the contacting system during the test; and
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a conductive path disposed along the first direction along a second plane that is parallel to the first plane, the conductive path coupling the closing terminal and the probe card, wherein a first portion of the conductive path is configured to be straight and parallel to the contacting system, wherein the first portion extends along the first distance between the needle probe card and the closing terminal (Fig. 1 annotated);
wherein the contacting system is configured to:
receive an electrical current existing from the first power semiconductor device during the test, wherein the closing terminal is configured to receive the electrical current flowing into the contacting system (Fig. 1, the electrical circuit 90 represents the electrical path) [claim 2];
a first end of the conductive path is arranged to be connected to the closing terminal (120); and
a second end of the conductive path, opposite the first end, is arranged to be connected to the probe card (Fig. 1, item 104) [claim 3];
wherein the contact conductive portion (220) and a wafer housing (202) that holds the wafer during the test are made of at least two separate elements, the closing contact conductive portion is stably bound in contact with the wafer housing portion (Fig. 2) [claim 5];
wherein the closing contact conductive portion (220) includes a housing to accommodate the wafer housing conductive portion (202) (Fig. 4, the test electrical circuit closing contact conductive portions (220) are formed on substrate, which accommodate the wafer housing conductive portion 202) [claim 6];
wherein the surface of the closing contact conductive portion and a surface of the wafer housing conductive portion are on the first plane (Fig. 2, the upper surface of the closing contact portion 220 is on the same plane with the wafer 40) [claim 7];
wherein the closing contact conductive portion is made of a same conductive material as the wafer housing conductive portion (implicit, para. 53) [claim 9]; and
wherein the contacting system further comprises a wafer housing conductive portion comprising a contacting disk (Fig, 3, item 200) [claim 10].
Regarding claims 15-16 and 19-20, Negishi teaches a contacting system for use with a test system that executes, on at least a first power semiconductor device, a test comprising a high-voltage or a high-current test function (para. 2), the contacting 200_ comprising:
a wafer housing conductive portion (200) configured to house a wafer to be contacted via a plurality of needles of a needle probe card (104) during tests, wherein the wafer includes a plurality of power semiconductor devices that includes the first power semiconductor device (para. 37);
a closing contact conductive portion (220) being electrically connected to the wafer housing conductive portion, wherein a surface of the closing contact conductive portion shares a common plane with a surface of the wafer housed in the wafer housing conductive portion (Fig. 2, the wafer 40 shares a common plane with the closing contact portion 220);
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wherein, when the system is in use, the closing contact conductive portion is brought into contact with a closing terminal of the test system (120) such that the closing contact conductive portion is parallel to a second plane along a conductive path of the test system extends in a first direction, and
wherein the conductive path coupled the closing terminal of the test system to the needle probe card of the test system (Fig. 1, annotated);
wherein the contacting system has a shape and extension (204) such that a conduction path is formed between the first power semiconductor device and the closing terminal (Fig. 3),
the current conduction path is distinct from the conduction path between the plurality of needles and the closing terminal and the current conduction path is straight and continuous and extends along a direction that is parallel or coincident with the first direction (para. 27, the current 92 may flow in any suitable direction, distinct from the conduction path 90) [claim 16];
wherein the closing contact conductive portion (220) and the wafer housing conductive portion (200) are made of two separate elements, and
the closing contact conductive portion is stably bound in contact with the wafer housing conductive portion (Figs. 3-4) [claim 19]; and
wherein the closing contact conductive portion (220) includes a housing to accommodate the wafer housing conductive portion (202) (Fig. 4, the test electrical circuit closing contact conductive portions (220) are formed on substrate, which accommodate the wafer housing conductive portion 202) [claim 20];
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 8 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Negishi.
Regarding claims 4 and 18, Negishi teaches all the claimed limitations except for said test electrical circuit closing contact conductive portion and said wafer housing conductive portion are made in one piece, however it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make said test electrical circuit closing contact conductive portion and said wafer housing conductive portion are made in one piece, since it has been held that forming in one piece a structure which has formerly been formed in two, or more pieces, involves only routine skill in the art. In re Larson, 144 USPQ 347, 349 (CCPA 1965).
Regarding claims 8 and 17, Negishi teaches the invention as claimed in claim 1 above. Negishi further teach said contacting system has a shape of a triangle (Fig. 3). Negish, however, does not specifically teach the one of more vertices of the triangle are rounded, and said wafer housing conductive portion of the contacting system is arranged at one of said vertices of the triangle, and it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the shape of said contacting system as claimed, since it has been held by the courts that a change in shape or configuration, without any criticality, is nothing more than one of numerous shapes that one of ordinary skill in the art will find obvious to provide based on the suitability for the intended final application. See In re Dailey, 149 USPQ 47 (CCPA 1976). It appears that the disclosed device would perform equally well shaped as disclosed by Negishi.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Negishi in view of Japanese Publication (JP4482061, hereinafter “JP4482061”).
Regarding claims 11-14, Negishi teaches all the claimed limitations except for the following: a handling system arranged to move said contacting system, so that, at least one at a time, all of the power semiconductor devices of the wafer arranged on said wafer housing conductive portion are placed in contact with said plurality of needles so as to be under test; wherein, at any position into which said contacting system is moved by the handling system, said at least one test electrical circuit closing terminal is arranged in contact with said test electrical circuit closing contact conductive portion of said contacting system [claim 11]; wherein said handling system is arranged to move said contacting system according to three movement directions orthogonal to each other [claim 12]; wherein said handling system is arranged to move said contacting system according to a pre-established path [claim 13] and wherein said pre-established path is stored in a suitable storage means associated with, or comprised in, said test system [claim 14].
JP4482061 teaches a test system comprises a handling system (51) arranged to move said contacting system, so that, at least one at a time, all of the power semiconductor devices of the wafer arranged on said wafer housing conductive portion are placed in contact with said plurality of needles so as to be under test; wherein, at any position into which said contacting system is moved by the handling system, said at least one test electrical circuit closing terminal is arranged in contact with said test electrical circuit closing contact conductive portion of said contacting system; wherein said handling system is arranged to move said contacting system according to three movement directions orthogonal to each other (the stage 57 is movable in 3 axis directions, para. 70) wherein said handling system is arranged to move said contacting system according to a pre-established path and wherein said pre-established path is stored in a suitable storage means associated with, or comprised in, said test system (S103, para. 84).
It would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to incorporate a handling system as taught within Negishi’s test system in order to facilitate an automated positioning of the probes on the wafer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH Q PHAN whose telephone number is (571)270-3898. The examiner can normally be reached Mon-Fri 9am-5pm.
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MINH Q. PHAN
Primary Examiner
Art Unit 2852
/MINH Q PHAN/ Primary Examiner, Art Unit 2852
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