DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-3, and 5-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over multiple embodiments of Guo et al. (CN 114241978 A1, hereinafter referred as “Guo”).
Regarding claim 1, Fig. 3 embodiment of Guo discloses pixel driving circuit, comprising: a drive transistor (DT), a light-emitting device (D1), a data writing subcircuit (T7), a conduction control subcircuit (T2), a coupling subcircuit (Cst1, Cst2),… and a second light-emitting control subcircuit (T5) (Fig. 3); wherein
the drive transistor (DT) is configured to generate a drive current according to a drive signal (Fig. 3 and ¶0057-¶0060 discloses driving module 50 generates driving current according to the data voltage Data stored by the first storage module 10);
the conduction control subcircuit (T2) is coupled to a gate of the drive transistor (DT) and a first node (N2) (Fig. 3), and is configured to, in response to a signal at a first light-emitting control signal terminal (EM1), make conduction between the gate of the drive transistor (DT) and the first node (N2) (¶0068 and ¶0071 disclose second transistor T2 responds to EM1 to connect or disconnect gate G of the driving transistor DT and the node N2 connected the storage module 10);
the data writing subcircuit (T7) is coupled to the first node (N2) (Fig. 3), and is configured to, in response to a signal at a scanning signal terminal (Scan), write the drive signal into the first node (N2) (¶0056 and ¶0084-¶0085 discloses T7 turns on in response to Scan and writes data to Cst1 at node N2);
the coupling subcircuit (Cst1, Cst2) is coupled to the first node (N2) and a second electrode of the drive transistor (DT), and is configured to store the drive signal and a threshold voltage of the drive transistor (DT) (¶0051, ¶0055-¶0056 and ¶0084 discloses first storage module Cst1 stores Data and the second storage module Cst2 stores the threshold voltage Vth);… and
the second light-emitting control subcircuit (T5) is coupled between the second electrode of the drive transistor (DT) and the light-emitting device (D1) (Fig. 3), and is configured to, in response to the signal at the first light-emitting control signal terminal (EM1), make conduction between the second electrode of the drive transistor (DT) and the light-emitting device (D1) (¶0076-¶0077 discloses T5 responds to EM1 to connect or disconnect drive module 50 and D1).
Fig. 3 embodiment of Guo doesn’t disclose a first light-emitting control subcircuit; and the first light-emitting control subcircuit is coupled to a first electrode of the drive transistor, and is configured to, in response to a signal at a second light-emitting control signal terminal, provide a signal at a first power supply terminal to the first electrode of the drive transistor.
However, Fig. 6 embodiment of Guo discloses a first light-emitting control subcircuit (T6); and the first light-emitting control subcircuit (T6) is coupled to a first electrode of the drive transistor (DT) (Fig. 6), and is configured to, in response to a signal at a second light-emitting control signal terminal (EM2), provide a signal at a first power supply terminal (VDD) to the first electrode of the drive transistor (DT) (¶0082-¶0083 discloses module 90/T6 responds to EM2 to apply VDD to the first electrode of the drive module 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fig. 3 embodiment of Guo in order to permit independent control of the VDD side connection of the drive transistor, allowing VDD to be supplied during threshold compensation and emission but isolated during data writing (¶0100-¶0103).
Regarding claim 2, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 1, wherein the second light-emitting control subcircuit (T5) comprises: a first transistor (T5) (Fig. 3); wherein a control terminal of the first transistor (T5) is coupled to the first light-emitting control signal terminal (EM1), a first terminal of the first transistor (T5) is coupled to the second electrode of the drive transistor (DT), and a second terminal of the first transistor (T5) is coupled to the light-emitting device (D1) (Fig. 3).
Regarding claim 3, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 1, wherein the drive transistor (DT) is a single-gate transistor (Fig. 3 illustrates a single-gate transistor of driving module 50) or a double-gate transistor; wherein when the drive transistor (DT) is the double-gate transistor, a first gate of the drive transistor (DT) is coupled to the conduction control subcircuit (T2), and a second gate of the drive transistor (DT) is coupled to the second electrode of the drive transistor (DT).
Regarding claim 5, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 1, wherein the data writing subcircuit (T7) comprises: a second transistor (T7); wherein a control terminal of the second transistor (T7) is coupled to the scanning signal terminal (Scan), a first terminal of the second transistor (T7) is coupled to a data signal terminal (Data), and a second terminal of the second transistor (T7) is coupled to the first node (N2) (Fig. 3).
Regarding claim 6, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 1, wherein the conduction control subcircuit (T2) comprises: a third transistor (T2); wherein a control terminal of the third transistor (T2) is coupled to the first light-emitting control signal terminal (EM1), a first terminal of the third transistor (T2) is coupled to the gate of the drive transistor (DT), and a second terminal of the third transistor (T2) is coupled to the first node (N2) (Fig. 3).
Regarding claim 7, Fig. 3 embodiment of Guo doesn’t disclose the pixel driving circuit according to claim 1, wherein the first light-emitting control subcircuit comprises: a fourth transistor; wherein a control terminal of the fourth transistor is coupled to the second light-emitting control signal terminal, a first terminal of the fourth transistor is coupled to the first power supply terminal, and a second terminal of the fourth transistor is coupled to the first electrode of the drive transistor.
However, Fig. 6 embodiment of Guo discloses wherein the first light-emitting control subcircuit comprises: a fourth transistor (T6); wherein a control terminal of the fourth transistor (T6) is coupled to the second light-emitting control signal terminal (EM2), a first terminal of the fourth transistor (T6) is coupled to the first power supply terminal (VDD), and a second terminal of the fourth transistor (T6) is coupled to the first electrode of the drive transistor (DT) (Fig. 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fig. 3 embodiment of Guo in order to permit independent control of the VDD side connection of the drive transistor, allowing VDD to be supplied during threshold compensation and emission but isolated during data writing (¶0100-¶0103).
Regarding claim 8, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 1, wherein the coupling subcircuit (Cst1, Cst2) comprises: a second capacitor (Cst2) and a third capacitor (Cst1); wherein a first terminal of the second capacitor (Cst2) is coupled to a second terminal of the third capacitor (Cst1), and a second terminal of the second capacitor (Cst2) is coupled to the second electrode of the drive transistor (DT) (Fig. 3); and a first terminal of the third capacitor (Cst1) is coupled to the first node (N2) (Fig. 3).
Regarding claim 9, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 1, further comprising: a first reset subcircuit (T1); wherein the first reset subcircuit (T1) is coupled to the gate of the drive transistor (DT), and is configured to, in response to a signal at a first reset signal terminal (ResetA), provide a signal at a first initialization signal terminal (Vcom/N1) to the gate of the drive transistor (DT) (Fig. 3).
Regarding claim 10, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 9, wherein the first reset subcircuit comprises: a fifth transistor (T1); wherein a control terminal of the fifth transistor (T1) is coupled to the first reset signal terminal (ResetA), a first terminal of the fifth transistor (T1) is coupled to the first initialization signal terminal (Vcom/N1), and a second terminal of the fifth transistor (T1) is coupled to the gate of the drive transistor (DT) (Fig. 3).
Regarding claim 11, Fig. 3 embodiment of Guo discloses the pixel driving circuit according claim1, further comprising: a second reset subcircuit (T4); wherein the second reset subcircuit (T4) is connected to the coupling subcircuit (Cst1, Cst2) (Fig. 3, ¶0035-¶0036 and ¶0103 disclose when T4 and T5 are conductive module 80 is in communication with the Cst2 and the driving transistor DT), and is configured to, in response to a signal at a second reset signal terminal (ResetB), provide a signal at a second initialization signal terminal (Vref) to the second electrode of the drive transistor (DT) (Fig. 3 and ¶0101-¶0103 disclose during initialization, ResetB turns T4 on and Vref is written to point S through T4 and T5).
Regarding claim 12, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 11, wherein the second reset subcircuit (T4) comprises: a sixth transistor (T4); wherein a control terminal of the sixth transistor (T4) is coupled to the second reset signal terminal (ResetB), a first terminal of the sixth transistor (T4) is coupled to an anode of the light-emitting device (D1), and a second terminal of the sixth transistor (T4) is coupled to the second initialization signal terminal (Vref) (Fig. 3).
Regarding claim 13, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 11, wherein the second reset subcircuit comprises: an eighth transistor (T4); wherein a control terminal of the eighth transistor (T4) is coupled to the second reset signal terminal (ResetB), a first terminal of the eighth transistor (T4) is coupled to the second electrode of the drive transistor (DT) (Fig. 3 and ¶0101-¶0103 disclose during initialization, ResetB turns T4 on and Vref is written to point S through T4 and T5), and a second terminal of the eighth transistor (T4) is coupled to the second initialization signal terminal (Vref) (Fig. 3).
Regarding claim 14, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim1, further comprising: a third reset subcircuit (T8); wherein the third reset subcircuit (T8) is coupled to the first terminal of the second capacitor (Cst2), and is configured to, in response to a signal at a first reset signal terminal (ResetA), provide a signal at a first initialization signal terminal (Vcom) to the first terminal of the second capacitor (Cst2) (Fig. 3).
Regarding claim 15, Fig. 3 embodiment of Guo discloses the pixel driving circuit according to claim 14, wherein the third reset subcircuit (T8) comprises: a seventh transistor (T8); wherein a control terminal of the seventh transistor (T8) is coupled to the first reset signal terminal (ResetA), a first terminal of the seventh transistor (T8) is coupled to the first terminal of the second capacitor (Cst2), and a second terminal of the seventh transistor (T8) is coupled to the first initialization signal terminal (Vcom) (Fig. 3).
4. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over multiple embodiments of Guo and in further view of Cai et al. (US 2018/0218681 A1, hereinafter referred as “Cai”).
Regarding claim 4, Guo as modified doesn’t disclose the pixel driving circuit according to claim 1, further comprising: a first capacitor; wherein a first terminal of the first capacitor is coupled to the first power supply terminal, and a second terminal of the first capacitor is coupled to the second electrode of the drive transistor.
However, in the same field of endeavor, Cai discloses a first capacitor (C2); wherein a first terminal of the first capacitor (C2) is coupled to the first power supply terminal (Vdd), and a second terminal of the first capacitor (C2) is coupled to the second electrode of the drive transistor (T1)(Fig. 6 and ¶0094 discloses the AMOLED pixel driver circuit further comprises a second capacitor C2, with one end connected to the drain of the first TFT T1 and the positive terminal Vdd of the DC power supply, and the other end connected to the source of the first TFT T1 and the second node b).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Guo in order to in order to reduce changes in the drive transistor source voltage caused by transitions of the data signal on my thereby stabilizing the stored compensation voltage and improving display accuracy.
5. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over multiple embodiments of Guo and in further view of Park et al. (US 2022/0157908 A1, hereinafter referred as “Park”).
Regarding claim 16, Fig. 3 embodiment of Guo discloses the display panel, comprising: the pixel driving circuit comprises: a first transistor (T5) and a third transistor (T2), and a control terminal of the first transistor (T5) is coupled to a control terminal of the third transistor (T2) (Fig. 3 illustrates the gates of T2 and T5 are commonly coupled to the EM1 control signal).
Guo doesn’t disclose a base substrate, comprising a plurality of sub-pixels, wherein the plurality of sub-pixels each comprise a pixel driving circuit according to claim 1;… an orthographic projection of an active layer of the first transistor on the base substrate has a first overlapping region with an orthographic projection of a first signal line on the base substrate, wherein the first signal line in the first overlapping region is a gate of the first transistor; and an orthographic projection of an active layer of the third transistor on the base substrate has a second overlapping region with the orthographic projection of the first signal line on the base substrate, wherein the first signal line in the second overlapping region is a gate of the third transistor.
However, in the same field of endeavor, Park discloses a base substrate (SUB), comprising a plurality of sub-pixels (Fig. 1 and ¶0039 discloses a pixel Px of the organic light emitting diode display according to the exemplary embodiment includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7), wherein the plurality of sub-pixels each comprise a pixel driving circuit (¶0060 discloses the organic light emitting diode display according to the exemplary embodiment includes a substrate (SUB), the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7) according to claim 1;… an orthographic projection of an active layer of the first transistor (T6) on the base substrate (SUB) has a first overlapping region with an orthographic projection of a first signal line (G6) on the base substrate (SUB) (Figs. 2-3 and ¶0083 disclose the sixth channel C6, which is a channel region of the sixth active pattern A6, overlaps the sixth gate electrode G6 and is between the sixth source electrode S6 and the sixth drain electrode D6), wherein the first signal line in the first overlapping region is a gate of the first transistor (T6) (Fig.2 and ¶0083 disclose sixth gate electrode G6); and an orthographic projection of an active layer of the third transistor (T5) on the base substrate (SUB) has a second overlapping region with the orthographic projection of the first signal line (G5) on the base substrate (SUB) (Figs. 2-3 and ¶0080 discloses the fifth channel C5, which is a channel region of the fifth active pattern A5, overlaps the fifth gate electrode G5 and is between the fifth source electrode S5 and the fifth drain electrode D5), wherein the first signal line in the second overlapping region is a gate of the third transistor (¶0080 discloses gate electrode G5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Guo in order to provide a compact layout arrangement and reducing separate gate routing structures.
Allowable Subject Matter
6. Claims 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ghebretinsae, Temesghen can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2626
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