Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-21 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1).
Regarding claims 1 and 20: Hanrieder discloses a high speed non-volatile electronic memory configuration (200, FIG. 2) comprising:
a short-term holding memory (volatile memory 202, FIG. 2) that holds predetermined configuration data, (stored data, par. 25); a long-term holding memory (non-volatile memory 204, FIG. 2); the ability to detect when a power supply voltage drops to a value lower than a constant voltage (power level detector 208 detects power supply Vdd outside operating voltage range, par. 31, and once the power supply is restored to the operating voltage level, par. 33); and a power supply monitoring circuit (power detector 208) that supplies a predetermined detection signal (power indicator signal PI, par. 33, FIG. 1) to the semiconductor integrated circuit in a case where it is detected that the power supply voltage is dropped to a value lower than the constant voltage (power level detector 208 detects power supply Vdd outside operating voltage range, par. 31).
Hanrieder does not disclose a short-term holding memory that has a data holding time shorter than a predetermined time and a long-term memory that has a data holding time being the predetermined time.
Ravindranath does disclose a memory manager (102, FIG. 1) where a short-term holding memory that has a data holding time shorter than a predetermined time (transient memory holds data for a short time relative to others, par. 13) and a long-term memory that has a data holding time being the predetermined time (static memory holds data for a longer time compared to transient memory, par. 13).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Hanrieder with the configuration of Ravindranath to have specify the short term volatile memory and long term nonvolatile memory to have the relative holding times.
Hanrieder and Ravindranath do not disclose the long-term memory holds specific data indicating whether or not a power supply voltage is recovered after dropping to a value lower than a constant voltage.
Atri discloses a power loss recovery mechanism that where long term memory holds specific data (power loss recovery PLR data, par. 15) indicating whether or not a power supply voltage is recovered (status bit of PLR on power-up indicates a power loss occurs during operation, then restores the data of the volatile memory once power is restored, par. 18) after dropping to a value lower than a constant voltage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder and Ravindranath with the configuration of Atri to allow the long term memory to hold the specific data that relates to the status of power loss to the system and the contents of the memory during power restoration.
Claim(s) 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Davis et al. (US 20030023923 A1).
Regarding claim 2: Hanrieder, Ravindranath and Atri do not disclose the short-term holding memory is one of a magneto-resistive random access memory (MRAM) and a non-volatile static random access memory (SRAM), and the long-term holding memory is also one of the MRAM and the SRAM.
Davis does disclose a magneto-resistive solid-state storage device (MRAM) where the short-term holding memory is one of a magneto-resistive random access memory (MRAM) (MRAM suitable for both short term… storage applications, par. 2 and 62) and a non-volatile static random access memory (SRAM), and the long-term holding memory is also one of the MRAM (MRAM suitable for… long term storage applications, par. 2 and 62) and the SRAM.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri with the configuration of Davis to allow the short term and long term memories to be of the magneto-resistive RAM.
Regarding claim 3: Hanrieder, Ravindranath and Atri do not disclose each of the short-term holding memory and the long-term holding memory includes a memory cell disposed at an intersection of a bit line and a word line. Davis does disclose a magneto-resistive solid-state storage device (MRAM) where each of the short-term holding memory and the long-term holding memory (e.g. MRAM 1, FIG. 1) includes a memory cell (storage cells 16, FIG. 1) disposed at an intersection of a bit line (14, FIG. 1) and a word line (12, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri with the configuration of Davis to have the specified structure for the memories.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1).
Regarding claim 4: Hanrieder, Ravindranath, and Atri do not disclose a check circuit that determines whether or not at least a part of the configuration data is lost and outputs a determination result.
Kow does disclose a method of recovering from a soft error withing a configured programmable device, comprising: a check circuit (error detection circuit 100, FIG. 1) that determines whether or not at least a part of the configuration data is lost (performs a cyclic redundancy check (CRC) to generate a checksum for the stored data, comparing to an initial “golden” CRC to detect errors and corrupted data) and outputs a determination result (error detection flag, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri with the checksum system of Kow to be able to monitor and determine if any data is lost upon a power supply shut down and restoration.
Claim(s) 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1), in further view of Kohda et al. (US 5467457 A).
Regarding claim 5: Hanrieder, Ravindranath, Atri, and Kow do not disclose the short-term holding memory includes a plurality of memory cells that holds a same value and the check circuit determines whether or not all held values of the plurality of memory cells coincide with each other.
Kohda does disclose a semiconductor memory device (FIG. 1), wherein the short-term holding memory includes a plurality of memory cells (plurality of memory cells of memory array 5, FIG. 1) that holds a same value (fixed data designated as either ‘0’ or ‘1’, col. 2 ll. 6-9) and the check circuit (coincidence detection circuit, FIG. 3) determines whether or not all held values of the plurality of memory cells coincide with each other (coincidence detection circuit outputs a coincidence detection signal when assigned address logic value matches the designated value, thus they are the same, col. 7 ll. 6-17).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri and Kow with the coincidence check system of Kohda to determine the reliability of the memory during operation.
Regarding claim 6: Hanrieder, Ravindranath, Atri, and Kow do not disclose the short-term holding memory includes a plurality of first memory cells that holds a first logical value and a plurality of second memory cells that holds a second logical value different from the first logical value, and the check circuit determines whether or not all held values of the plurality of first memory cells coincide with each other and all the held values of the plurality of second memory cells coincide with each other.
Kohda does disclose a semiconductor memory device (FIG. 1), wherein the short-term holding memory includes a plurality of first memory cells (plurality of memory cells of memory blocks of memory array 5, FIG. 12) that holds a first logical value (fixed data designated logical value ‘0’ or ‘1’, col. 2 ll. 6-9, FIG. 1) and a plurality of second memory cells (different memory block than first, FIG. 12) that holds a second logical value different from the first logical value (fixed data designated logical value ‘0’ or ‘1’, col. 2 ll. 6-9, FIG. 1), and
the check circuit (coincidence detection circuit, FIG. 3) determines whether or not all held values of the plurality of first memory cells coincide with each other and all the held values of the plurality of second memory cells coincide with each other (for each memory block, coincidence detection circuit outputs a coincidence detection signal when assigned address logic value matches the designated value, col. 7 ll. 6-17).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri and Kow with the coincidence check system of Kohda to determine the reliability of the memory during operation.
Claim(s) 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1), in further view of Busch (US 20110110129 A1).
Regarding claim 10: Hanrieder, Ravindranath, and Atri do not disclose a check circuit that determines whether or not at least a part of the configuration data is lost and outputs a determination result; and an auxiliary power supply unit that supplies a predetermined auxiliary voltage when the power supply voltage is shut off.
Kow does disclose a method of recovering from a soft error withing a configured programmable device, comprising: a check circuit (error detection circuit 100, FIG. 1) that determines whether or not at least a part of the configuration data is lost (performs a cyclic redundancy check (CRC) to generate a checksum for the stored data, comparing to an initial “golden” CRC to detect errors and corrupted data) and outputs a determination result (error detection flag, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri with the checksum system of Kow to be able to monitor and determine if any data is lost upon a power supply shut down and restoration.
Hanrieder, Ravindranath, Atri, and Kow do not disclose an auxiliary power supply unit that supplies a predetermined auxiliary voltage when the power supply voltage is shut off.
Busch does disclose a circuit arrangement for a power-supply unit comprising: an auxiliary power supply unit (16, FIG. 4) that supplies a predetermined auxiliary voltage when the power supply voltage is shut off (supplies auxiliary power to device when main power is decreased in sleep or standby, par. 72).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri, and Kow with the auxiliary power supply unit of Busch to allow the system a backup power source in case of a power shut down.
Regarding claim 11: Hanrieder, Ravindranath, Atri, and Kow do not disclose the auxiliary power supply unit includes a diode and a capacitive element connected in series to the power supply voltage.
Busch does disclose the auxiliary power supply unit includes a diode (D3, FIG. 4) and a capacitive element (C5, FIG. 4) connected in series to the power supply voltage (auxiliary output voltage, FIG. 4).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri and Kow with the configuration of Busch to have the structure of the auxiliary power supply unit of the claimed invention.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1), in further view of Busch (US 20110110129 A1), in further view of Umeyama (US 20160134159 A1).
Regarding claim 12: Hanrieder, Ravindranath, Atri, Kow, and Busch do not disclose the auxiliary power supply unit further includes a primary battery that supplies the auxiliary voltage.
Umeyama discloses a semiconductor integrated circuit included a power supply circuit, wherein the auxiliary power supply unit (220, FIG. 1) further includes a primary battery (221, FIG. 1) that supplies the auxiliary voltage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri, Kow, and Busch with the configuration of Umeyama to have the same structure of the claimed invention.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1), in further view of Busch (US 20110110129 A1), in further view of Schutt et al. (US 20190217706 A1).
Regarding claim 13: Hanrieder, Ravindranath, Atri, Kow, and Busch do not disclose the auxiliary power supply unit further includes an energy harvester that performs energy harvesting.
Schutt does disclose a vehicle electrical power supply with an auxiliary power supply source, wherein the auxiliary power supply unit (32, FIG. 1) further includes an energy harvester (alternate charging arrangement 42 connected to auxiliary power source 32 can be an energy harvester, par. 15) that performs energy harvesting.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri, Kow, and Busch with the energy harvester configuration of Schutt to allow the system to have an energy harvester to match the structure of the claimed invention.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1), in further view of Busch (US 20110110129 A1), in further view of Schutt et al. (US 20190217706 A1), in further view of Wu et al. (US 20170257023 A1).
Regarding claim 14: Hanrieder, Ravindranath, Atri, Kow, Busch, and Schutt do not disclose the auxiliary power supply unit further includes a secondary battery that is charged with power from the energy harvester and is discharged when the power supply voltage is shut off.
Wu does disclose an energy harvester implementation wherein the auxiliary power supply unit further includes a secondary battery (second battery power BAT, which can be a rechargeable battery, par. 20) that is charged with power from the energy harvester (200, during energy harvest mode 200A-200B, FIG. 2A-2B) and is discharged when the power supply voltage is shut off (during moments of low power levels, secondary power source supports first power source and system to continue operation, par. 33, FIG. 2C).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri, Kow, Busch, and Schutt with the energy harvester configuration of Wu to allow the secondary battery to have a charge method utilizing the energy harvester.
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1), in further view of Busch (US 20110110129 A1, in further view of Radecker et al (US 20060285366 A1).
Regarding claim 15: Hanrieder, Ravindranath, Atri, Kow, and Busch do not disclose a resonance circuit that generates a transient voltage that fluctuates with a lapse of time when the auxiliary voltage is supplied, wherein the check circuit compares an absolute value of the transient voltage with a predetermined reference voltage and outputs a result of the comparison as the determination result.
Radecker does disclose a control circuit for a switch unit with a resonant transformer, comprising a resonance circuit (resonance circuit of resonance transformer arrangement 170, par. 333, FIG. 1C) that generates a transient voltage (auxiliary signal from resonance transformer arrangement, par. 36) that fluctuates with a lapse of time when the auxiliary voltage is supplied (auxiliary signal exhibits fixed phase in relation to a load alternating current, thus fluctuating, par. 36), wherein the check circuit (phase detector 376f, FIG. 3, 930, FIG. 9) compares an absolute value of the transient voltage with a predetermined reference voltage (auxiliary voltage is compared to a predefined reference value, par. 289) and outputs a result of the comparison as the determination result (an output regarding the reference crossing moments of the phase detector to be sent to a synchronizer, par. 38).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri, Kow, and Busch with the system of Radecker to monitor the fluctuating transient voltage along the predetermined voltage at intervals to check for reliability.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kow et al. (US 8010871 B1), in further view of Busch (US 20110110129 A1, in further view of Badtke (EP 1160637 A1).
Regarding claim 16: Hanrieder, Ravindranath, Atri, Kow, and Busch do not disclose a real time clock that generates predetermined time information, wherein the check circuit causes the long-term holding memory to hold time information when the power supply voltage is shut off, and determine whether or not a difference between a time indicated by the held time information and a time indicated by newly generated time information exceeds a predetermined threshold when the power supply voltage is recovered.
Bradtke does disclose a method of checking the plausibility of time information provided by a battery backed up real time clock (RTC) comprising a real time clock (real time clock RTC, par. 3) that generates predetermined time information (RTC providing real time information, par. 4), wherein the check circuit causes the long-term holding memory to hold time information when the power supply voltage is shut off (regularly storing time information of RTC in NVM which can occur before system shut down, step S5 of FIG. 1), and determine whether or not a difference between a time indicated by the held time information (stored time in NVM, TIMENVM) and a time indicated by newly generated time information (current time from RTC, TIMERTC) exceeds a predetermined threshold when the power supply voltage is recovered (after system boot S1 of FIG. 1, checking if TIMERTC exceeds a threshold time consisting of TIMENVM plus a “best case back up time” TIMEBCB, step S42 of FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, Atri, Kow, and Busch with the clock system of Bradtke to have a method of checking reliability of the clock signal when the power of the system shuts down and restores.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Kim et al. (US 20150043295 A1).
Regarding claim 17: Hanrieder, Ravindranath, and Atri do not disclose the short-term holding memory includes first and second short-term holding memories having different data holding times.
Kim does disclose a method for refreshing volatile memory wherein the short-term holding memory (volatile memory 300, FIG. 3) includes first and second short-term holding memories (standard memory cells and weak memory cells, par. 36) having different data holding times (weak cells have a shorter retention times compared to standard memory cells, par. 36).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri with the configuration of Kim to allow the volatile memory to have different sets of short term memory with their own retention holding times for operation.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Rau et al. (US 6222757 B1).
Regarding claim 18: Hanrieder, Ravindranath, and Atri do not disclose the semiconductor integrated circuit is a field- programmable gate array (FPGA), the configuration data includes wire connection information of a logical block and connection information of a switch block, the short-term holding memory is disposed in the logical block and the switch block, and the long-term holding memory is disposed in the logical block.
Rau does disclose a configuration of an FPGA wherein the semiconductor integrated circuit is a field-programmable gate array (FPGA) (FIG. 1 and 6), the configuration data includes wire connection information of a logical block and connection information of a switch block (configuration data for logic signals to be coupled to the switches in the logic blocks and define the functionality of the FGPA, col. 2 ll. 38-45), the short-term holding memory (volatile SRAM memory cells, FIG. 5) is disposed in the logical block (memory cells places anywhere in the logic block, col. 2 ll. 1-3, col. 17 ll. 16-22), and the switch block (memory cells placed close to switches, col. 1 ll. 60-61, col. 17 ll. 16-22), and the long-term holding memory (nonvolatile memory cells, e.g., EEPROM cells, col. 18 ll. 62-64) is disposed in the logical block (col. 19 ll. 9-13).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri with the configuration of Rau to have the structure of the claimed invention.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Mizuta et al. (US 20040073837 A1).
Regarding claim 19: Hanrieder, Ravindranath, and Atri do not disclose the semiconductor integrated circuit is a large scale integration (LSI), and the short-term holding memory is disposed in a predetermined register.
Mizuta does disclose a semiconductor device wherein the semiconductor integrated circuit is a large scale integration (LSI) (system LSI 10, FIG. 1), and the short-term holding memory is disposed in a predetermined register (CPU 11 of device reads internal data or programs in registers 23 and 25, par. 38 and 50).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri with the configuration of Mizuta to have the same structure of the claimed invention.
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Hanrieder et al. (US 20050091547 A1) in view of Ravindranath et al. (US 2010/0235603 A1), in further view of Atri et al (US 20060059385 A1), in further view of Yu et al. (US 6651172 B1).
Regarding claim 21: Hanrieder, Ravindranath, and Atri do not disclose a read only memory that holds initial configuration data; and a configuration controller that reads the initial configuration data from the read only memory and supplies the initial configuration data to the semiconductor integrated circuit.
Yu does disclose a method for initializing a data processing system with configuration data comprising: a read only memory (external EEPROM 200, FIG. 2) that holds initial configuration data (EEPROM stores configuration information 202, FIG. 2); and a configuration controller (EEPROM logic 102) that reads the initial configuration data from the read only memory (enables interface 10 to read the configuration information from EEPROM 200) and supplies the initial configuration data to the semiconductor integrated circuit (configuration information to be used by interface 10, col. 4 ll. 49-60).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Hanrieder, Ravindranath, and Atri to allow the system an external ROM to initialize the configuration data for the integrated circuit like the claimed invention.
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a power supply shutoff recovery control unit that transits to: a write state in which the specific data having a value different from an initial value is held in the long-term holding memory in a case where the power supply voltage drops to a value lower than the constant voltage; a read state in which the specific data is read from the long-term holding memory in a case where the power supply voltage recovers to a value higher than the constant voltage; a check state in which the determination result is acquired in a case where the specific data that is read is not the initial value; and a reconfiguration state in which predetermined initial configuration data is held in the short-term holding memory as new configuration data in a case where at least a part of the configuration data is lost as in claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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