DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the first initial voltage terminal" in lines 4 and 5 of claim 3. No prior recitation of “a first initial voltage terminal” was presented in this claim or claims 1 and 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination the Office will interpret this claim as intending to recite “a first initial voltage terminal”.
Claim 13 recites the limitation “the second control terminal” in line 4. No prior recitation of “a second control terminal” is presented in this claims or claim 1. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination the Office will interpret this claim as intending to recite “a second control terminal”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8, 9, 11, 19, 20, 22-25, and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chinese Pub. No. CN 111223444 A by Liu (“Liu”).
As to claim 1, Liu discloses a pixel circuit (Liu, pixel circuit, Figure 1), comprising a first light emitting control circuit (Liu, fourth switch T4, Figure 1), a light emitting element (Liu, light-emitting device D, Figure 1), a driving circuit (Liu, third switch T3, Figure 1) and a light emitting gating circuit (Liu, light emission duration control module 102, Figure 1); wherein
the first light emitting control circuit is electrically connected to a first light emitting control terminal (Liu, gate of the fourth switch T4 is connected to the third light-emitting control signal EMC, Figure 1, ¶ [0059]), a first voltage terminal (Liu, first power supply voltage terminal VDD, Figure 1) and a first terminal of the driving circuit (Liu, top terminal of third switch T3 connected to the fourth switch T4, Figure 1) respectively, and is configured to control the connection between the first voltage terminal (Liu, first power supply voltage terminal VDD, Figure 1) and the first terminal of the driving circuit (Liu, top terminal of third switch T3, Figure 1) under the control of a first light emitting control signal provided by the first light emitting control terminal during a light emitting phase; As shown in figure 2 of Liu, during light emission stage S3, EMC is low which turns on the fourth switch T4 to connect VDD to the third switch T3.
a second terminal of the driving circuit (Liu, bottom terminal of third switch T3, Figure 1) is electrically connected to a first electrode of the light emitting element (Liu, top electrode of light-emitting device D, Figure 1), and the driving circuit is configured to drive the light emitting element; As shown in figure 1 of Liu, the third switch T3 connects through the sixth switch T6 to drive the light-emitting device D.
the light emitting gating circuit (Liu, light emission duration control module 102, Figure 1) is configured to control, under the control of a first control signal provided by the first control terminal (Liu, gate-B terminal, Figure 1), according to a light emitting data voltage provided by the light emitting data voltage terminal (Liu, Data-T, Figure 1), to form a current path between the second terminal of the driving circuit (Liu, bottom terminal of third switch T3, Figure 1) and the light emitting element (Liu, light-emitting device D, Figure 1) in the light emitting phase under the control of a light emitting control voltage provided by the light emitting control voltage terminal (Liu, second light emission control signal terminal EM2, Figure 1), to control the driving circuit to control the light emitting element to emit light, or to control to form the current path between the second terminal of the driving circuit and the light emitting element in the light emitting phase, to control the driving circuit to control the light emitting element to emit light, or to control to generate the current path between the second terminal of the driving circuit and the light emitting element in the light emitting phase under the control of the first light emitting control signal, to control the driving circuit to control the light emitting element to emit light. As shown in figure 2 of Liu, the light emission phase S3 is shown where the light-emitting device D emits light. In addition, as shown in figure 1 of Liu, the connection of the third switch T3 to the light-emitting device D is controlled by the state of the sixth switch T6.
As to claim 2, Liu discloses the pixel circuit wherein the light emitting gating circuit (Liu, light emission duration control module 102, Figure 1) includes a second light emitting control circuit (Liu, sixth switch T6, Figure 1) and a first gating control circuit (Liu, switches T7, T8, T9, and second capacitor C2, Figure 1);
the first gating control circuit (Liu, switches T7, T8, T9, and second capacitor C2, Figure 1) is electrically connected to the first control terminal (Liu, gate-B terminal, Figure 1), the light emitting data voltage terminal (Liu, Data-T, Figure 1), a gating control terminal (Liu, second node N2, Figure 1), a second light emitting control terminal (Liu, gate terminal of switch T6, Figure 1), a light emitting control voltage terminal (Liu, second light emission control signal terminal EM2, Figure 1) and the first light emitting control terminal (Liu, first and third light-emitting control signal EMC/EM1, Figure 1, ¶ [0059]) (Liu, the third light emission control signal terminal EMC and the first light emission control signal terminal EM1 can be shared. Figure 1, ¶ [0059]) respectively, and is configured to write a light emitting data voltage provided by the light emitting data voltage terminal into the gating control terminal under the control of the first control signal, and control the second light emitting control terminal to be connected to the light emitting control voltage terminal or to be connected to the first light emitting control terminal under the control of a potential of the gating control terminal; As shown in figure 1 of Liu, based on the input signal being high or low to the gate terminal switch T9, the Data-T signal is provided to the second node N2 which then controls the switches T7 and T8 to provide a signal to the gate terminal of the switch T6.
the second light emitting control circuit (Liu, sixth switch T6, Figure 1) is electrically connected to the second light emitting control terminal (Liu, gate terminal of switch T6, Figure 1), the second terminal of the driving circuit (Liu, bottom terminal of third switch T3, Figure 1) and the first electrode of the light emitting element (Liu, top electrode of light-emitting device D, Figure 1) respectively, and is configured to control the second terminal of the driving circuit to be connected to the first electrode of the light emitting element under the control of a potential of the second light emitting control terminal; As shown in figure 1 of Liu, the connection of the third switch T3 to the light-emitting device D is controlled by the state of the sixth switch T6.
a second electrode of the light emitting element is electrically connected to the second voltage terminal (Liu, second power supply voltage terminal VSS, Figure 1).
As to claim 3, Liu discloses the pixel circuit wherein the light emitting gating circuit (Liu, light emission duration control module 102, Figure 1) further comprises a first capacitor (Liu, second capacitor C2, Figure 1);
a first terminal of the first capacitor (Liu, top electrode of second capacitor C2, Figure 1) is electrically connected to the gating control terminal (Liu, second node N2, Figure 1), and a second terminal of the first capacitor (Liu, bottom electrode of second capacitor C2, Figure 1) is electrically connected to the first initial voltage terminal (Liu, VCOM, Figure 1).
As to claim 4, Liu discloses the pixel circuit wherein the first gating control circuit (Liu, switches T7, T8, T9, and second capacitor C2, Figure 1) comprises a first transistor (Liu, ninth switch T9, Figure 1), a second transistor (Liu, seventh switch T7, Figure 1) and a third transistor (Liu, eighth switch T8, Figure 1);
a control electrode of the first transistor (Liu, ninth switch T9, Figure 1) is electrically connected to the first control terminal (Liu, gate-B terminal, Figure 1), a first electrode of the first transistor is electrically connected to the light emitting data voltage terminal (Liu, Data-T, Figure 1), and a second electrode of the first transistor is electrically connected to the gating control terminal (Liu, second node N2, Figure 1);
a control electrode of the second transistor (Liu, seventh switch T7, Figure 1) is electrically connected to the gating control terminal (Liu, second node N2, Figure 1), a first electrode of the second transistor is electrically connected to the light emitting control voltage terminal (Liu, second light emission control signal terminal EM2, Figure 1), and a second electrode of the second transistor is electrically connected to the second light emitting control terminal (Liu, gate terminal of switch T6, Figure 1);
a control electrode of the third transistor (Liu, eighth switch T8, Figure 1)is electrically connected to the gating control terminal (Liu, second node N2, Figure 1), a first electrode of the third transistor is electrically connected to the first light emitting control terminal (Liu, first and third light-emitting control signal EMC/EM1, Figure 1, ¶ [0059]), and a second electrode of the third transistor is electrically connected to the second light emitting control terminal (Liu, gate terminal of switch T6, Figure 1).
As to claim 5, Liu discloses the pixel circuit wherein the second light emitting control circuit comprises a fourth transistor (Liu, sixth switch T6, Figure 1);
a control electrode of the fourth transistor (Liu, sixth switch T6, Figure 1) is electrically connected to the second light emitting control terminal (Liu, gate terminal of switch T6, Figure 1), a first electrode of the fourth transistor is electrically connected to the second terminal of the driving circuit (Liu, bottom electrode of third switch T3 is connected to the top electrode of sixth switch T6, Figure 1), and a second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element (Liu, light-emitting device D, Figure 1).
As to claim 8, Liu discloses the pixel circuit wherein the light emitting gating circuit (Liu, light emission duration control module 102, Figure 1) includes a second gating control circuit (Liu, ninth switch T9, Figure 1), a third light emitting control circuit (Liu, eighth switch T8, Figure 1) and a fourth light emitting control circuit (Liu, seventh switch T7, Figure 1);
the second gating control circuit (Liu, ninth switch T9, Figure 1) is electrically connected to the first control terminal (Liu, gate-B terminal, Figure 1), the light emitting data voltage terminal (Liu, Data-T, Figure 1) and the gating control terminal (Liu, second node N2, Figure 1) respectively, and is configured to write the light emitting data voltage into the gating control terminal under the control of the first control signal; As shown in figure 1 of Liu, based on the gate-B signal, the ninth switch T9 connects Data-T to the second node N2.
the third light emitting control circuit (Liu, eighth switch T8, Figure 1) is electrically connected to the gating control terminal (Liu, second node N2, Figure 1), the second electrode of the light emitting element (Liu, light-emitting device D, Figure 1) and the second voltage terminal (Liu, second power supply voltage terminal VSS, Figure 1) respectively, and is configured to control the connection between the second electrode of the light emitting element and the second voltage terminal under the control of the potential of the gating control terminal; As shown in figure 1 of Liu, the eighth switch T8 connects to the light-emitting device D and VSS through the sixth switch T6.
the fourth light emitting control circuit (Liu, seventh switch T7, Figure 1) is electrically connected to the light emitting control voltage terminal (Liu, second light emission control signal terminal EM2, Figure 1), the second electrode of the light emitting element (Liu, light-emitting device D, Figure 1) and the second voltage terminal (Liu, second power supply voltage terminal VSS, Figure 1) respectively, and is configured to control the connection between the second electrode of the light emitting element and the second voltage terminal under the control of the light emitting control voltage provided by the light emitting control voltage terminal. As shown in figure 1 of Liu, the seventh switch T7 connects to the light-emitting device D and VSS through the sixth switch T6.
As to claim 9, Liu discloses the pixel circuit further comprising a fifth light emitting control circuit (Liu, switches T1, T2, and T5, Figure 1); wherein
the fifth light emitting control circuit (Liu, switches T1, T2, and T5, Figure 1)is electrically connected to the first light emitting control terminal (Liu, first and third light-emitting control signal EMC/EM1, Figure 1, ¶ [0059]), the second terminal of the driving circuit (Liu, bottom terminal of third switch T3, Figure 1) and the first electrode of the light emitting element (Liu, top electrode of light-emitting device D, Figure 1) respectively, and is configured to control the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the first light emitting control signal; or
wherein the light emitting gating circuit further comprises a second capacitor; a first terminal of the second capacitor is electrically connected to the gating control terminal, a second terminal of the second capacitor is electrically connected to the first initial voltage terminal.
As to claim 11, Liu discloses the pixel circuit wherein the second gating control circuit includes a fifth transistor (Liu, ninth switch T9, Figure 1), the third light emitting control circuit includes a sixth transistor (Liu, eighth switch T8, Figure 1), and the fourth light emitting control circuit includes a seventh transistor (Liu, seventh switch T7, Figure 1);
a control electrode of the fifth transistor (Liu, ninth switch T9, Figure 1is electrically connected to the first control terminal (Liu, gate-B terminal, Figure 1), a first electrode of the fifth transistor is electrically connected to the light emitting data voltage terminal (Liu, Data-T, Figure 1), and a second electrode of the fifth transistor is electrically connected to the gating control terminal (Liu, second node N2, Figure 1);
a control electrode of the sixth transistor (Liu, eighth switch T8, Figure 1) is electrically connected to the gating control terminal (Liu, second node N2, Figure 1), a first electrode of the sixth transistor is electrically connected to the second electrode of the light emitting element (Liu, top electrode of light-emitting device D, Figure 1), and a second electrode of the sixth transistor is electrically connected to the second voltage terminal (Liu, second power supply voltage terminal VSS, Figure 1); As shown in figure 1 of Liu, the eighth switch T8 connects to the light-emitting device D and VSS through the sixth switch T6.
a control electrode of the seventh transistor (Liu, seventh switch T7, Figure 1) is electrically connected to the light emitting control voltage terminal (Liu, second light emission control signal terminal EM2, Figure 1), a first electrode of the seventh transistor is electrically connected to the second electrode of the light emitting element (Liu, top electrode of light-emitting device D, Figure 1), and a second electrode of the seventh transistor is electrically connected to the second voltage terminal (Liu, second power supply voltage terminal VSS, Figure 1), As shown in figure 1 of Liu, the seventh switch T7 connects to the light-emitting device D and VSS through the sixth switch T6.
wherein the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor, and the fifth transistor is an n-type transistor; or the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor (Liu, the seventh switch T7 can be a P-type switch and eighth switch T8 can be an N-type switch, Figure 1, ¶ [0063]), and the fifth transistor is a p-type transistor (Liu, the ninth switch T9 is the same type as seventh switch T7 which is a P-type as shown in figure 1); or, the seventh transistor is an n-type transistor, the sixth transistor is a p-type transistor, and the fifth transistor is an n-type transistor; or, the seventh transistor is an n-tvpe transistor, the sixth transistor is a p-tvpe transistor. and the fifth transistor is a p-tvpe transistor.
As to claim 19, Liu discloses a pixel driving method (Liu, pixel driving circuit and driving method, ¶ [0001]), applied to the pixel circuit according to claim 1, the pixel driving method comprising:
in the light emitting phase (Liu, light emission stage S3, Figure 2), controlling, by the first light emitting control circuit (Liu, fourth switch T4, Figure 1), the first voltage terminal (Liu, VDD, Figure 1) to be connected to the first terminal of the driving circuit (Liu, top electrode of third switch T3, Figure 1) under the control of the first light emitting control signal (Liu, EMC, Figure 1); As shown in figures 1 and 2 of Liu, when the EMC signal is low (in the light emission stage S3), the switch T4 passes VDD to the top electrode of switch T3.
controlling, by the light emitting gating circuit (Liu, light emission duration control module 102, Figure 1), under the control of the first control signal (Liu, Gate-B, Figure 1), according to the light emitting data voltage (Liu, Data-T, Figure 1), during the light emitting phase and under the control of the light emitting control voltage provided by the light emitting control voltage terminal, to generate the current path between the second terminal of the driving circuit and the light emitting element, to control the driving circuit to control the light emitting element to emit light, or to generate the current path between the second terminal of the driving circuit and the light emitting element during the light emitting phase, so as to control the driving circuit to control the light emitting element to emit light. As shown in figure 2 of Liu, the light emission phase S3 is shown where the light-emitting device D emits light. In addition, as shown in figure 1 of Liu, the connection of the third switch T3 to the light-emitting device D is controlled by the state of the sixth switch T6.
As to claim 20, Liu discloses the pixel driving method wherein the light emitting gating circuit (Liu, light emission duration control module 102, Figure 1) includes a second light emitting control circuit (Liu, sixth switch T6, Figure 1) and a first gating control circuit (Liu, switches T7, T8, T9, and second capacitor C2, Figure 1); and the pixel driving method includes:
writing, by the first gating control circuit, under the control of the first control signal (Liu, Gate-B, Figure 1), the light emitting data voltage (Liu, Data-T, Figure 1) into the gating control terminal (Liu, second node N2, Figure 1), and, under the control of the potential of the gating control terminal, controlling the second light emitting control terminal (Liu, gate terminal of switch T6, Figure 1) to be connected to the light emitting control voltage terminal (Liu, second light emission control signal terminal EM2, Figure 1), or controlling the second light emitting control terminal to be connected to the first light emitting control terminal (Liu, first and third light-emitting control signal EMC/EM1, Figure 1, ¶ [0059]);
controlling, by the second light emitting control circuit (Liu, sixth switch T6, Figure 1), the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the potential of the second light emitting control terminal; As shown in figure 1 of Liu, the sixth switch T6 activates to connect the third switch T3 and the light-emitting device D.
or
wherein the light emitting gating circuit includes a second patina control circuit, a third light emitting control circuit and a fourth light emitting control circuit; and the pixel driving method includes: writing, by the second gating control circuit, the light emitting control voltage into the patina control terminal under the control of the first control signal:
controlling, by the third light emitting control circuit, the second electrode of the light emitting element to be connected to the second voltage terminal under the control of the potential of the gating control terminal:
controlling, by the fourth light emitting control circuit, the second electrode of the light emitting element to be connected to the second voltage terminal under the control of the light emitting control voltage.
As to claim 22, Liu discloses the pixel driving method applied to the pixel circuit according to claim_1, wherein the display period includes a first phase (Liu, S1 and S2, Figure 2) and a light emitting phase (Liu, light emission stage S3, Figure 2) which are arranged successively; the pixel driving method includes:
in the first phase, writing, by the light emitting gating circuit (Liu, light emission duration control module 102, Figure 1), the light emitting data voltage provided by the light emitting data voltage terminal (Liu, Data-T, Figure 1) under the control of the first control signal (Liu, Gate-B, Figure 1); controlling, by the first light emitting control circuit, the first voltage terminal (Liu, VDD, Figure 1) to be disconnected from the first terminal of the driving circuit under the control of the first light emitting control signal; During the phases S1 and S2, the EMC is high, which blocks VDD by T4 to T3.
in the light emitting phase, controlling, by the first light emitting control circuit (Liu, fourth switch T4, Figure 1), the first voltage terminal to be connected to the first terminal of the driving circuit under the control of the first light emitting control signal; In phase S3, the EMC signal is low which enables T4 to transmit VDD to T3.
in the light emitting phase, controlling, by the light emitting gating circuit, to generate the current path between the second terminal of the driving circuit and the light emitting element according to the light emitting data voltage and under the control of the light emitting control voltage provided by the light emitting control voltage terminal, to control the driving circuit to control the light emitting element to emit light, or controlling, by the light emitting gating circuit, to generate the current path between the second terminal of the driving circuit and the light emitting element under the control of the first light emitting control signal, to control the driving circuit to control the light emitting element to emit light. In phase S3, the switch T6 is activated to provide signals from switch T3 to the light emitting device D.
As to claim 23, Liu discloses the pixel driving method wherein in the light emitting phase, both the first light emitting control signal and the light emitting control voltage are square wave voltage signals. As shown in figure 2 of Liu, the waveform for all the signals are in square waveforms.
As to claim 24, Liu discloses the pixel driving method wherein the light emitting gating circuit includes a second light emitting control circuit (Liu, sixth switch T6, Figure 1) and a first gating control circuit (Liu, switches T7, T8, T9, and second capacitor C2, Figure 1); the pixel driving method includes: in a first display mode,
in the first phase (Liu, S1 and S2, Figure 2), writing, by the first gating control circuit, the light emitting data voltage into the gating control terminal under the control of the first control signal, and controlling, by the first gating control circuit, the second light emitting control terminal to be connected to the first light emitting control terminal under the control of the potential of the gating control terminal; As shown in figure 2 of Liu, during the stage S2, the switch T9 loads the Data-T as the Gate-B signal is low.
in the light emitting phase (Liu, S3, Figure 2), when the first light emitting control signal is a valid voltage signal, controlling, by the first light emitting control circuit (Liu, T4, Figure 1), the connection between the first voltage terminal (Liu, VDD, Figure 1) and the first terminal of the driving circuit under the control of the first light emitting control signal (Liu, EMC, Figure 1), and controlling, by the second light emitting control circuit, the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the first light emitting control signal, and driving, by the driving circuit, the light emitting element to emit light. As shown in figures 1 and 2 of Liu, during the phase S3, EMC is low which causes the switch T4 to send VDD to switch T3, T6, and then the light emitting device D.
As to claim 25, Liu discloses the pixel driving method wherein the light emitting gating circuit comprises a second light emitting control circuit (Liu, sixth switch T6, Figure 1) and a first gating control circuit (Liu, switches T7, T8, T9, and second capacitor C2, Figure 1); the pixel driving method comprises: in a second display mode,
in the first phase (Liu, S1 and S2, Figure 2), writing, by the first gating control circuit, the light emitting data voltage into the gating control terminal tinder the control of the first control signal, and controlling, by the first gating control circuit, the connection between the second light emitting control terminal and the light emitting control voltage terminal under the control of the potential of the gating control terminal; As shown in figure 2 of Liu, during the stage S2, the switch T9 loads the Data-T as the Gate-B signal is low.
in the light emitting phase, when the first light emitting control signal is a valid voltage signal, controlling, by the first light emitting control circuit, the first voltage terminal to be connected to the first terminal of the driving circuit under the control of the first light emitting control signal; As shown in figures 1 and 2 of Liu, during the phase S3, EMC is low which causes the switch T4 to send VDD to switch T3, T6, and then the light emitting device D.
in the light emitting phase, when the light emitting control voltage (Liu, second light emission control signal terminal EM2, Figure 1) is a valid voltage, controlling, by the second light emitting control circuit, under the control of the first light emitting control signal, the second terminal of the driving circuit to be connected to the first electrode of the light emitting element, and driving, by the driving circuit, the light emitting element to emit light; when the light emitting control voltage is an invalid voltage, controlling, by the second light emitting control circuit, under the control of the first light emitting control signal, the second terminal of the driving circuit to be disconnected from the first electrode of the light emitting element. When EM2 is an invalid voltage level, the switch T6 is off and blocks the signals to the light emitting device D.
As to claim 32, Liu discloses a display device comprising the pixel circuit according to claim 1 (Liu, pixel driving circuit and driving method, display device, ¶ [0001]).
Allowable Subject Matter
Claims 6, 13, 14, 26, and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 6, Liu (Chinese Pub. No. CN 111223444 A) discloses the pixel circuit wherein the first transistor (Liu, ninth switch T9, Figure 1) is an n-type transistor, the second transistor (Liu, seventh switch T7, Figure 1) is a p-type transistor, and the third transistor (Liu, eighth switch T8, Figure 1) is an n-type transistor (Liu, the seventh switch T7 can be a P-type switch and eighth switch T8 can be an N-type switch, Figure 1, ¶ [0063]); or,
the first transistor is an n-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor; or,
the first transistor is a p-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor,
wherein when the second transistor is a p-type transistor and the third transistor is an n-type transistor, a width-to-length ratio of a channel of the third transistor is greater than a width-to-length ratio of a channel of the second transistor.
Liu does not expressly teach
first transistor is an n-type transistor;
or,
the first transistor is an n-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor; or,
the first transistor is a p-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor,
wherein when the second transistor is a p-type transistor and the third transistor is an n-type transistor, a width-to-length ratio of a channel of the third transistor is greater than a width-to-length ratio of a channel of the second transistor.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to claim 13, Liu (Chinese Pub. No. CN 111223444 A) discloses the pixel circuit further comprising a data writing-in circuit (Liu, second switch T2, Figure 1), a compensation control circuit (Liu, fifth switch T5, Figure 1), a first initialization circuit (Liu, first switch T1, Figure 1), a second initialization circuit and a third capacitor (Liu, C1, Figure 1); wherein
the data writing-in circuit (Liu, second switch T2, Figure 1) is electrically connected to the second control terminal (Liu, Gate-A, Figure 1), a data line (Liu, Data-I, Figure 1) and the first terminal of the driving circuit (Liu, top terminal of the third switch T3, Figure 1) respectively, and is configured to write a data voltage provided by the data line into the first terminal of the driving circuit under the control of the second control signal provided by the second control terminal;
the compensation control circuit (Liu, fifth switch T5, Figure 1) is electrically connected to a third control terminal (Liu, Gate-A, Figure 1), the control terminal of the driving circuit (Liu, first node N1, Figure 1) and the second terminal of the driving circuit (Liu, bottom terminal of the third switch T3, Figure 1) respectively, and is configured to control the communication between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of a third control signal provided by the third control terminal;
the first initialization circuit (Liu, first switch T1, Figure 1) is electrically connected to a first reset control terminal (Liu, RST, Figure 1), the control terminal of the driving circuit (Liu, first node N1, Figure 1) and a third initial voltage terminal (Liu, Vint, Figure 1) respectively, and is configured to write a third initial voltage provided by the third initial voltage terminal into the control terminal of the driving circuit under the control of a first reset control signal provided by the first reset control terminal;
a first terminal of the third capacitor (Liu, C1, Figure 1) is electrically connected to the control terminal of the driving circuit (Liu, first node N1, Figure 1), and a second terminal of the third capacitor is electrically connected to the first voltage terminal (Liu, VDD, Figure 1).
Liu does not expressly teach
a second initialization circuit;
the second initialization circuit is electrically connected to a second reset control terminal, the first electrode of the light emitting element and a fourth initial voltage terminal respectively, and is configured to write a fourth initial voltage provided by the fourth initial voltage terminal into the first electrode of the light emitting element under the control of a second reset control signal provided by the second reset control terminal;
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to dependent claim 14, this claim depends upon objected dependent claim 13 and objected to for the same reasons.
As to claim 26, Liu (Chinese Pub. No. CN 111223444 A) does not expressly disclose the pixel driving method wherein a frequency of the first light emitting control signal is less than a frequency of the light emitting control voltage;
in the display period, a time length during which a potential of the first light emitting control signal continues to be an invalid voltage is shorter than a time length during which the light emitting control voltage continues to be an invalid voltage,
wherein a frequency of the light emitting control voltage is greater than or equal to twice a frequency of the first light emitting control signal,
in the display period, a time length during which the potential of the first light emitting control signal continues to be the valid voltage is greater than 2xt1+t2: wherein t1 is a time during which the light emitting control voltage continues to be a valid voltage, and t2 is a time during which the light emitting control voltage continues to be an invalid voltage,
a pixel density of the pixel circuit included in a display panel is less than or equal to a pixel density threshold.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to claim 30, Liu (Chinese Pub. No. CN 111223444 A) does not expressly disclose the pixel driving method wherein the frequency of the first light emitting control signal is equal to the frequency of the light emitting control voltage;
in the display period, a time length during which the potential of the first light emitting control signal continues to be an invalid voltage is shorter than a time length during which the light emitting control voltage continues to be an invalid voltage,
wherein a pixel density of the pixel circuit included in the display panel is greater than a pixel density threshold.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Pub. No. 2022/0005403 by Yue et al. teaches a pixel circuit with a similar pixel circuit.
U.S. Pub. No. 2022/0301492 by Yuan et al. teaches a pixel driving circuit, pixel driving method, display panel and display device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT D CASTIAUX whose telephone number is (571)272-5143. The examiner can normally be reached Mon-Fri 7:30 AM- 4:00 PM.
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623
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