DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/30/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6 and 12-16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claimed subject matter is directed to software per se.
Claims 1 and 12 are directed to an interface system (for configuring memory placement in a computing device) and a tuning tool (for an audio system). The claims further recite the limitations such as “a communication protocol for”, “a memory placement request”, “a graphical user interface” and “a configuration data generated by the graphical user interface”.
According to MPEP § 2111: During patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." The Federal Circuit’s en banc decision in Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005) expressly recognized that the USPTO employs the "broadest reasonable interpretation" standard:
The Patent and Trademark Office ("PTO") determines the scope of claims in patent applications not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction "in light of the specification as it would be interpreted by one of ordinary skill in the art." In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364[, 70 USPQ2d 1827, 1830] (Fed. Cir. 2004). Indeed, the rules of the PTO require that application claims must "conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description." 37 CFR 1.75(d)(1).
See also In re Suitco Surface, Inc., 603 F.3d 1255, 1259, 94 USPQ2d 1640, 1643 (Fed. Cir. 2010); In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000).
As noted above, the claims recites various elements for performing functionality of receiving a memory layout, displaying a configuration, an instruction to modify the configuration and generating modified configuration data and displaying the data. All of the elements such as “a memory placement request”, “a graphical user interface” and “a configuration data generated by the graphical user interface” can be considered as software and “a communication protocol” can be interpreted as rules, standards or specifications which can implemented using software, hardware or combination of both. Therefore, according to BRI, the claims can be interpreted to comprise software only and the software is not patentable category.
The dependent claims fail to cure the deficiencies of the parent claims and thus rejected under same rationales as applied to rejected parent claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by over Koh et al. (US 7,584,465).
As per claim 1, Koh teaches an interface system for configuring memory placement in a computing device having a plurality of processing modules, the plurality of processing modules each have data to be stored in a plurality of memory locations of the computing device to be accessed and communicated to a system for execution (Koh: col. 1, lines 23-32: “an embedded system may have digital signal processors (DSPs), where each processor may contain on-chip RAM and/or ROM memory. Furthermore, each DSP may also access external memory and the multiple DSPs may share the same external memory”), the interface system comprising:
a communication protocol for receiving a memory layout from the computing device (Koh: col. 14, lines 46-64: “The memory information 260 may be one or more files generated by a configuration environment of the memory mapping generator 250 or may otherwise be configured in the memory mapping generator 250. The memory mapping generator 250 may obtain the memory information 260 from an interface or API call”);
a graphical user interface for displaying a configuration for each of the plurality of processing modules to a memory location within the memory layout (Koh: col. 22, lines 40-66: “the graphical user interface may allow the user to select user preferred mappings to map the named memory sections to the memory structure of the target device”);
a memory placement request for a modification to the configuration, the memory placement request is entered by a user at the graphical user interface (Koh: col. 22, lines 40-66: “the graphical user interface may allow the user to edit or otherwise re-arrange the optimizations provided by the memory mapping generator 250. In this manner, the user can exercise control over the optimization on a granular basis”) and correlates a processing module with a latency level for a memory location in the plurality of memory locations (Koh: col. 18, lines 11-67: “For example, the memory with the shortest access delay and on a processor may be the first memory to be assigned a code or data segment…The method at step 330 determines the memory section available with the fastest access time (or smallest wait state) and that has memory space available for the code or data segment of the selected named section. In this case, memory Bank A is the fastest memory with space available for Section Code 1”); and
a configuration data generated at the graphical user interface; the configuration data represents placement of data to be stored in the plurality of memory locations based on the memory placement request for each processing module (Koh: col. 22. Line 40 – col. 23, line 25: “In a further embodiment, the graphical user interface may allow the user to edit or otherwise re-arrange the optimizations provided by the memory mapping generator 250. In this manner, the user can exercise control over the optimization on a granular basis. The optimizations selected by the user then would be incorporated in either the memory mapping 270 provided to the automatic code generator 210 or otherwise implemented in the linker command files 224 to build the program 230…The graphical modeling environment 520 may provide a configuration mechanism to include a component configuration block 530 in the block diagram model 215. The component configuration block 530 allows for registering the component types and the physical memory layout of the target device. Furthermore, the component configuration block 530 allows a user to specify custom memory mappings for generated code to the target device”) and a memory capacity of the computing device (Koh: col. 3, lines 29-40: “In another aspect, the memory information includes a description of one or more of the following: 1) a size of the memory element, 2) an access rate of the memory element, and 3) a configuration of the memory element. In a further aspect, the memory mapping is determined by applying a heuristic, an exhaustive, or a genetic type of optimization algorithm”; col. 14, lines 30-50: “The memory information 260 comprises a description of the attributes and physical layout of the memory elements of a computational hardware device, including on-chip memory of one or more processors and/or any external memory elements accessed by one or more processors. Each of these memory elements can be of different types with different access types and rates, configuration, size and other attributes. As such, the memory description 260 may comprise information describing the type of each memory, the access type and rate of each memory, the size of each memory and any other configuration of the memory that may impact the performance of a program 230 storing code and data segments on the one or more memory elements”).
As per claim 2, Koh teaches wherein the graphical user interface further comprises a plurality of options for the user to select the memory placement request wherein one or more user selected memory placement requests are used to generate the configuration data (Koh: col. 22, lines 40-66: “Additionally, either the memory mapping generator 250 or the automatic code generator 210 may provide a graphical user interface to allow a user to select one or more of the optimizations determined by the memory mapping generator 250 for any of the code and data memory sections of the program 230…the graphical user interface may allow the user to select user preferred mappings to map the named memory sections to the memory structure of the target device”).
As per claim 3, Koh teaches the interface system of claim 2, further comprising a consumption guide displaying consumption levels, at the graphical user interface, for one or more user selected memory placement requests (Koh: col. 19, lines 20-30; col. 26, lines 14-35: “the memory mapping graphical user interface 800 could display one or more optimized memory mappings 270 generated by the memory mapping generator 250”; displaying memory mapping means displaying allocated or consumed levels of memory).
As per claim 4, Koh teaches wherein the consumption levels are presented to the user for the user to input memory placement requests wherein the processing module having a highest priority may be allocated to a memory location that has a fastest fetch time of all the memory locations (Koh: col. 13, line 65 – col. 14, line 13: “Additionally, the program information 255 may assign a priority or some other weighted factor to each of the code and data segments in the program information 255”; col. 18, lines 33-54).
As per claim 5, Koh teaches wherein the graphical user interface sends the configuration data to the computing device over the communication protocol and the computing device further comprises: an allocator to allocate the data to the memory layout according to the configuration data (Koh: col. 7, line 65 – col. 8, line 17: “The linker-command file defines the memory mapping to direct the code and data segments of the uniquely named memory section for each block to be placed in the portions of memory as determined by the memory mapping”).
As per claim 6, Koh teaches The interface system of claim 5, further comprising a results profile displayed at the graphical user interface, the results profile indicates profiling results of the configuration of the memory layout as modified according to the configuration data, the profiling results are sent to the graphical user interface over the communication protocol (Koh: col. 20, lines 8-21: “The simulations on the program simulator 275 will produce profiles of execution times for each of the simulations associated with a version of a memory mapping 270. Then, at step 380, the memory mapping generator 250 can select the memory mapping 270 that provided the best performance based on the time results from the simulations on the program simulator 275”).
Claim 7 is directed to a method and it is similar in scope with the combination of claims 1 and 3 above. Since, Koh claim 1 teaches a method, claim 7 is rejected under same rationales as applied to claims 1 and 3 above.
Claim 8 is similar in scope with claim 2 above, thus claim 8 is rejected under same rationales as applied to claim 2 above.
Claim 9 is similar in scope with claim 5 above, thus claim 9 is rejected under same rationales as applied to claim 5 above.
Claim 10 is similar in scope with claim 6 above, thus claim 10 is rejected under same rationales as applied to claim 6 above.
Claim 11 is similar in scope with claim 4 above, thus claim 11 is rejected under same rationales as applied to claim 4 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Holladay et al. (US 2012/0047435) and further in view of Koh et al. (US 7,584,465).
As per claim 12, Holladay teaches a tuning tool for an audio system having a digital signal processor (DSP) and a plurality of audio modules controlled by the DSP (Holladay: par. [0076]: “DSP parameters and settings are associated with active (or powered) devices with processing capability. The system may automate configuration of a variety of possible connection scenarios of different combinations of audio devices…, and (3) tuning parameters or preset data”) the tuning tool comprising:
a communication protocol for communication between the tuning tool and the audio system (Holladay: par. [0079]: “The disclosed system provides a network-independent protocol to seamlessly integrate across a plurality of different AV-related devices of varying complexity using any of a variety of physical networks and communication platforms. In addition, the system allows for upgrades, changes and additions of AV-related devices within the system without additional software programming by providing messaging functionality to discover those aspects of a particular AV-related device that are not already known. The messaging functionality also allows AV data and related information to be transmitted between selected, AV-related devices efficiently and with minimized network traffic”).
Holladay expressly fails to teach a graphical user interface receiving a memory layout of the DSP sent from the audio system, the graphical user interface displays a configuration of the memory layout; a memory placement request input by a user at the graphical user interface, the memory placement request modifies the configuration of the memory layout; and a configuration data generated by the graphical user interface, the configuration data represents modifications to an allocation of the audio modules in memory locations of the memory configuration based on the memory placement request and memory capacity of the DSP, the configuration data is displayed at the graphical user interface.
Koh teaches a graphical user interface receiving a memory layout of the DSP sent from the audio system, the graphical user interface displays a configuration of the memory layout (Koh: col. 22, lines 40-66: “the graphical user interface may allow the user to select user preferred mappings to map the named memory sections to the memory structure of the target device”); a memory placement request input by a user at the graphical user interface, the memory placement request modifies the configuration of the memory layout (Koh: col. 22. Line 40 – col. 23, line 25: “In a further embodiment, the graphical user interface may allow the user to edit or otherwise re-arrange the optimizations provided by the memory mapping generator 250. In this manner, the user can exercise control over the optimization on a granular basis. The optimizations selected by the user then would be incorporated in either the memory mapping 270 provided to the automatic code generator 210 or otherwise implemented in the linker command files 224 to build the program 230…The graphical modeling environment 520 may provide a configuration mechanism to include a component configuration block 530 in the block diagram model 215. The component configuration block 530 allows for registering the component types and the physical memory layout of the target device. Furthermore, the component configuration block 530 allows a user to specify custom memory mappings for generated code to the target device”); and a configuration data generated by the graphical user interface, the configuration data represents modifications to an allocation of the audio modules in memory locations of the memory configuration based on the memory placement request and memory capacity of the DSP, the configuration data is displayed at the graphical user interface (Koh: col. 3, lines 29-40: “In another aspect, the memory information includes a description of one or more of the following: 1) a size of the memory element, 2) an access rate of the memory element, and 3) a configuration of the memory element. In a further aspect, the memory mapping is determined by applying a heuristic, an exhaustive, or a genetic type of optimization algorithm”; col. 14, lines 30-50: “The memory information 260 comprises a description of the attributes and physical layout of the memory elements of a computational hardware device, including on-chip memory of one or more processors and/or any external memory elements accessed by one or more processors. Each of these memory elements can be of different types with different access types and rates, configuration, size and other attributes. As such, the memory description 260 may comprise information describing the type of each memory, the access type and rate of each memory, the size of each memory and any other configuration of the memory that may impact the performance of a program 230 storing code and data segments on the one or more memory elements”).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a graphical user interface receiving a memory layout of the DSP sent from the audio system, the graphical user interface displays a configuration of the memory layout; a memory placement request input by a user at the graphical user interface, the memory placement request modifies the configuration of the memory layout; and a configuration data generated by the graphical user interface, the configuration data represents modifications to an allocation of the audio modules in memory locations of the memory configuration based on the memory placement request and memory capacity of the DSP, the configuration data is displayed at the graphical user interface as taught by Koh in the system of Holladay to provide an intelligent and systematic approach to determining and generating memory mapping that improves the performance of the system (Koh: col. 2, lines 18-25).
As per claim 13, Holladay and Koh teach wherein the graphical user interface comprises a plurality of options for the user selection, one or more selections of user options from the plurality of options are used to generate the configuration data (Koh: col. 22, lines 40-66: “Additionally, either the memory mapping generator 250 or the automatic code generator 210 may provide a graphical user interface to allow a user to select one or more of the optimizations determined by the memory mapping generator 250 for any of the code and data memory sections of the program 230…the graphical user interface may allow the user to select user preferred mappings to map the named memory sections to the memory structure of the target device”).
As per claim 14, Holladay and Koh teach comprising a consumption guide displaying estimated consumption levels, at the graphical user interface, for one or more user selected memory placement requests (Koh: col. 19, lines 20-30; col. 26, lines 14-35: “the memory mapping graphical user interface 800 could display one or more optimized memory mappings 270 generated by the memory mapping generator 250”; displaying memory mapping means displaying allocated or consumed levels of memory).
As per claim 15, Holladay and Koh teach wherein the DSP further comprises an allocator, the graphical user interface sends the configuration data to the DSP over the communication protocol and the allocator in the DSP allocates the audio modules to be stored in the memory layout at corresponding memory locations according to the configuration data (Koh: col. 7, line 65 – col. 8, line 17: “The linker-command file defines the memory mapping to direct the code and data segments of the uniquely named memory section for each block to be placed in the portions of memory as determined by the memory mapping”).
As per claim 16, Holladay and Koh teach the tuning tool of claim 15, further comprising a results profile displayed at the graphical user interface, the results profile indicates profiling results of the configuration of the memory layout as modified according to the configuration data, the profiling results are sent to the graphical user interface over the communication protocol displayed as the results profile at the graphical user interface (Koh: col. 20, lines 8-21: “The simulations on the program simulator 275 will produce profiles of execution times for each of the simulations associated with a version of a memory mapping 270. Then, at step 380, the memory mapping generator 250 can select the memory mapping 270 that provided the best performance based on the time results from the simulations on the program simulator 275”).
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nijhawan et al. (US 7,577,813) teaches a system and a method of determining memory latency and allocating resources.
Allen et al. (US 2007/0073993) teaches a method of allocating memory based on weighted priority,
Koenen (US 2004/0019891) teaches allocating memory to improve performance by reducing access latency.
Davis et al. (US 2002/0087652) teaches a system for determining and grouping processor nodes and memory nodes to efficiently allocate memory based on the latency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim T Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138