DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claim(s) 1-17 and 22-24 are currently pending.
Claim(s) 22-24 have been withdrawn.
Claim(s) 18-21 have been canceled.
Election/Restrictions
Applicant’s election without traverse of Group 1 (claims 1-17) in the reply filed on 03/31/2026 is acknowledged.
Claims 22-24 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected solar cell (Group 2), there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0139764 A1, Smith in view of US 2012/0000522 A1, Dennis et al. (hereinafter “Dennis”).
Regarding claim 1
Loscutoff teaches a method for preparing a solar cell [Figs. 1-13 and para. 0014], comprising the following steps of:
providing a solar cell substrate (101) [Fig. 1 and para. 0015], the solar cell substrate (101) comprising an area A (see area noted as “A” in Fig. 8 below) subjected to a first treatment (corresponding to patterning of doped silicon dioxide layer 105 and texturization step of the front side surface of the substrate 101) [Figs. 5 and 8, paras. 0019 and 0026] and an area B (see area noted as “B” in Fig. 8 below) not subjected to the first treatment (area B is not subjected to the patterning and texturing process) [Figs. 1-13 and para. 0019];
performing the first treatment on the area A [Figs. 5 and 8, paras. 0019 and 0026], wherein the first treatment comprises one or more selected from a texturing process, an etching process, and a wrap-around removal process [paras. 0019 and 0026].
Smith does not teach forming a phosphorous-boron co-doped silicon oxide layer on the area B and instead discloses forming a phosphorus doped silicon oxide layer (phosphosilicate glass 107) [Fig. 6 and para. 0020].
Dennis teaches a solar cell wherein diffusion of N-type dopants is performed by forming a phosphorous-boron co-doped silicon oxide layer (borophosphosilicate glass BPSG), and wherein the phosphorous-boron co-doped silicon oxide layer is a thermally stable ink where the boron content can be optimized to encourage pushing of phosphorus into the doped region of the substrate while preventing or minimizing diffusion of N-type dopants into the P-type dopant regions [para. 0031].
Smith and Dennis are analogous inventions to methods of fabricating solar cells comprising forming diffusion regions using doped silicon oxide layers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the phosphorus doped silicon oxide layer (107) of Smith to comprise phosphorous-boron co-doped silicon oxide, as in Dennis, for the purpose of diffusing N-type dopants using a thermally stable ink that allows control and optimization of the diffusion of the phosphorus (through optimizing the boron content) while preventing or minimizing diffusion of N-type dopants into the P-type dopant regions [para. 0031].
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Fig. 5 (Left) and Fig. 8 (Right)
Regarding claim 15
Modified Smith teaches the method as set forth above, wherein the area A comprises the front surface of the silicon wafer substrate (101), the area B comprises a back surface of the silicon wafer substrate (101) [see Figs. 5 and 8 above], wherein
the solar cell substrate (101) is a silicon wafer substrate with a wrap-around layer (corresponding to thermally grown silicon oxide layer 102) on a front surface thereof [Figs. 2, 7 and 8, para. 0016];
the first treatment is the wrap-around removal process on the area A (see Fig. 8 wherein during the texturing step of the front surface, the thermal oxide layer 102 is removed) [Figs. 7-8, paras. 0016 and 0026].
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Dennis as applied to claims 1 and 15 above, and further in view of CN113745106A*, Lang et al.
*Cited in IDS.
Regarding claim 2
Modified Smith teaches the method as set forth above, wherein the solar cell substrate (101) is a silicon wafer substrate [para. 0015], the area A comprises a front surface of the silicon wafer substrate (corresponding to the front textured surface) and a partial area of a back surface of the silicon wafer substrate (corresponding to the portion denoted as A in Fig. 8 above), and the area B is an area of the back surface of the silicon wafer substrate that does not belong to the area A (see Fig. 8 above);
the first treatment comprises performing the texturing process on the area A of the front surface of the silicon wafer substrate with a chemical liquid for texturing he substrate 101 is textured with random pyramids using a wet etch process comprising potassium hydroxide and isopropyl alcohol) [para. 0026], and performing a patterning process on the area A of the back surface of the silicon wafer substrate (101) [para. 0019 and Fig. 5].
Modified Smith does not teach the patterning process on the area A of the back surface comprising an etching process.
Lang teaches that an etching process using a solution containing hydrogen fluoride can effectively remove borosilicate glass layers and the phosphorus-boron co-doped glass layers from the surface of a substrate, and will not cause surface defects due to incomplete cleaning or excessive corrosion [paras. 0004 and 0007-0010].
Modified Smith and Lang are analogous inventions in the field of methods for fabricating solar cells involving removal of doped silicon oxide glass layers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have patterned the area A of the back surface of the substrate of modified Smith using an etching process comprising a hydrogen fluoride (HF) solution, as discloses in Lang, as such is a known and effective method of removing such doped silicon oxide layers from the surface of silicon substrate, and because said etching process does not cause surface defects due to incomplete cleaning or excessive corrosion.
Regarding claim 12
Modified Smith teaches the method as set forth above, wherein after performing the first treatment on the area A, the method further comprises the following steps of:
removing the phosphorous-boron co-doped silicon oxide layer (107) on the area B (see opening of layers 105/107 in area B) [Smith, Fig. 13 and para. 0030-0031]; and
manufacturing a first electrode (113) on the area A of the back surface of the silicon wafer substrate (101) [Fig. 13 and paras. 0030-0031], and manufacturing a second electrode (112) on the area B of the back surface of the silicon wafer substrate (101) [Fig. 13 and paras. 0030-0031].
Regarding the limitation “removing the phosphorous-boron co-doped silicon oxide layer on the area B with a solution containing hydrogen fluoride”, as set forth above, Lang discloses that a solution containing hydrogen fluoride can effectively remove borosilicate glass layers and the phosphorus-boron co-doped glass layers from the surface of a substrate, and will not cause surface defects due to incomplete cleaning or excessive corrosion [paras. 0004 and 0007-0010].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have removed the phosphorus-boron co-doped silicon oxide layer on the area B with a solution containing hydrogen fluoride (HF), as discloses in Lang, as such is a known and effective method of removing such doped silicon oxide layers from the surface of silicon substrate, and because said etching process does not cause surface defects due to incomplete cleaning or excessive corrosion.
Allowable Subject Matter
Claims 3-11, 13, 14, 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3
The prior art of record, whether alone or in combination fails to teach that the formation of the phosphorous-boron co-doped silicon oxide layer on the area B comprises the steps of:
patterning the back surface of the silicon wafer substrate to remove a part of the phosphorous-boron co-doped silicon oxide layer, wherein an area of the back surface of the silicon wafer substrate corresponding to a remaining phosphorus-boron co-doped silicon oxide layer is the area B.
Modified Smith teaches that forming the phosphorous-boron co-doped silicon oxide layer (BPSG) on the area B comprises the steps of:
forming a phosphorous-boron co-doped silicon oxide layer (107) on the back surface of the silicon wafer substrate (101) [Smith. Fig. 6 and para. 0020; Dennis, para. 0031].
However, in modified Smith, it is the BSG layer (105) that is patterned/removed from the back surface. Accordingly, the prior art does not disclose patterning the back surface of the silicon wafer substrate to remove a part of the phosphorous-boron co-doped silicon oxide layer as required by the claim. Therefore, the claim is allowed.
Regarding claim 4
The prior art of record, whether alone or in combination fails to teach that the formation of the phosphorous-boron co-doped silicon oxide layer on the back surface of the silicon wafer substrate comprises the steps of:
forming a phosphorus-doped amorphous silicon film layer and a boron-doped silicon oxide layer sequentially on the back surface of the silicon wafer substrate; and
annealing the silicon wafer substrate, such that the phosphorus-doped amorphous silicon film layer is converted into a phosphorus-doped polycrystalline silicon film layer, and the boron-doped silicon oxide layer absorbs phosphorus elements to form the phosphorus-boron co-doped silicon oxide layer.
While Smith discloses forming a phosphorus doped silicon oxide film (107) and a boron doped silicon oxide film (105) on the bask surface of substrate (101), the prior art of record does not disclose annealing the silicon wafer substrate, such that the phosphorus-doped amorphous silicon film layer is converted into a phosphorus-doped polycrystalline silicon film layer, and the boron-doped silicon oxide layer absorbs phosphorus elements to form the phosphorus-boron co-doped silicon oxide layer. Furthermore, the cited art is silent to the phosphorus-doped film comprising amorphous silicon. Accordingly, the instant claim is allowed.
Regarding claims 5-8 and 11
Claims 5-8 and 11 are allowed for their dependency on claim 4.
Regarding claims 9-10
Claims 9-10 are allowed for their dependency on claim 3.
Regarding claim 13
Modified Smith teaches the method as set forth above, wherein prior to manufacturing the first electrode and the second electrode, the method further comprises a step of depositing a passivating oxide layer (110) on the front surface of the silicon wafer substrate (101) [Smith, Figs. 10-13 and para. 0028].
However, modified Smith does not teach a second passivating oxide film layer deposited on the back surface of the silicon wafer substrate. Furthermore, modified Smith does not teach the passivating oxide layer comprising aluminum oxide and, instead, discloses silicon oxide [Smith, para. 0028].
Furthermore, while modified Smith discloses the step of forming the front surface passivating oxide (110) performed prior to manufacturing the first electrode and the second electrode [Figs. 10-13 of Smith], modified Smith also does not teach the step of depositing the passivating oxide performed after removing the phosphorous-boron co-doped silicon oxide layer on the area B. As seen in Fig. 10 of Smith, said depositing step takes place prior to the removal of the phosphorous-boron co-doped silicon oxide layer on the area B.
Regarding claim 14
Claim 14 is allowed for their dependency on claim 13.
Regarding claim 16
The prior art of record, whether alone or in combination fails to teach that the formation of the phosphorous-boron co-doped silicon oxide layer on the area B comprises the steps of:
forming a phosphorus-doped amorphous silicon film layer and a boron-doped silicon oxide layer sequentially on the back surface of the silicon wafer substrate; and annealing the silicon wafer substrate, such that the phosphorus-doped amorphous silicon film layer is converted into a phosphorus-doped polycrystalline silicon film layer, and the boron-doped silicon oxide layer absorbs phosphorus elements to form the phosphorus-boron co-doped silicon oxide layer.
While Smith discloses forming a phosphorus doped silicon oxide film (107) and a boron doped silicon oxide film (105) on the bask surface of substrate (101), the prior art of record does not disclose annealing the silicon wafer substrate, such that the phosphorus-doped amorphous silicon film layer is converted into a phosphorus-doped polycrystalline silicon film layer, and the boron-doped silicon oxide layer absorbs phosphorus elements to form the phosphorus-boron co-doped silicon oxide layer. Furthermore, the cited art is silent to the phosphorus-doped film comprising amorphous silicon. Accordingly, the instant claim is allowed.
Regarding claim 17
Claim 17 is allowed for their dependency on claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2015/0075595 A1, Gall teaches a method for preparing a solar cell, comprising the following steps of:
providing a solar cell substrate (1) [Figs. 2A-2C and para. 0186], the solar cell substrate (1) comprising an area A (corresponding to front surface of substrate 1 and regions 10a) subjected to a first treatment (corresponding to chemical etching of the front surface F and to first laser irradiation step) and an area B (corresponding to regions 11b) not subjected to the first treatment (regions 11b are subjected to a separate/subsequent laser irradiation step) [paras. 0190, 0199 and 0203];
forming a phosphorous-boron co-doped layer on the area B (corresponding to layer 10b formed by laser irradiation of the silicon oxide doping layer 11 and the silicon oxide semiconductor layer 10 comprising an equilibrium concentration of boron and phosphorus) [paras. 0049-0050, 0093-0094, 0099-0100, 0172 and 0205]; and
performing the first treatment on the area A (10a) [paras. 0190 and 0199], wherein the first treatment comprises one or more selected from a texturing process, an etching process, and a wrap-around removal process [paras. 0190 and 0199].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAYLA GONZALEZ RAMOS whose telephone number is (571)272-5054. The examiner can normally be reached Monday - Thursday, 9:00-5:00 - EST.
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/MAYLA GONZALEZ RAMOS/Primary Examiner, Art Unit 1721
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