DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 21 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (US 2020/0343314).
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(Claim 1) Nakamura et al. teach a display substrate, comprising:
a base substrate, comprising a display area (71) and a peripheral area (72), the peripheral area at least partially surrounding the display area; and
a plurality of pixel units (PX) arranged in the display area of the base substrate, the plurality of pixel units being arranged in an array in the display area along a first direction (X) and a second direction (Y), at least one of the pixel units comprising a reflective bonding structure and an LED light-emitting unit, and the first direction intersecting with the second direction
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wherein the reflective bonding structure (89, paragraph 147) comprises:
a first electrode (conductive oxide shell of 89, paragraph 151) arranged on the base substrate (2);
a first reflective electrode (core of 89) arranged on a side of the first electrode away from the base substrate; and
a first bonding portion (lower half of #77 in the z-direction, paragraph 150) in the arranged on a side of the first reflective electrode (89) away from the base substrate; and
wherein the LED light-emitting unit (CHIP) comprises:
a second bonding portion (upper half of #77 in the z-direction) arranged on a side of the first bonding portion away from the base substrate;
an LED epitaxial layer (paragraph 116) arranged on a side of the second bonding portion away from the base substrate; and
a second electrode (88, paragraph 147) arranged on a side of the LED epitaxial layer (CHIP) away from the base substrate,
wherein an orthographic projection of the second bonding portion on the base substrate is located within an orthographic projection of the first bonding portion on the base substrate; and
wherein the first bonding portion and the second bonding portion comprise a same material.
(Claim 21) Nakamura et al. teach a display panel, comprising the display substrate (fig. 10, paragraph 208).
(Claim 22) Nakamura et al. teach a display device, comprising the display substrate (fig. 10, paragraph 264).
Allowable Subject Matter
Claims 2 – 14, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(Claim 2) wherein the first bonding portion and the second bonding portion comprise the same material selected from ITO or IZO.
(Claim 5) further comprising a partition between pixel units adjacent to each other, wherein the partition covers at least a part of a surface of the LED epitaxial layer away from the base substrate, a sidewall of the reflective bonding structure, and a sidewall of the LED light-emitting unit.
(Claim 11) further comprising a prism portion arranged on a side of the second electrode away from the base substrate,
wherein an orthographic projection of the prism portion on the base substrate at least partially overlaps with an orthographic projection of the LED epitaxial layer on the base substrate.
Claims 23 and 24 are allowable, because prior art do not teach:
(Claim 23) wherein the reflective bonding structure comprises a first electrode arranged in the first electrode material layer, a first reflective electrode arranged in the first reflective electrode material layer, and a first bonding portion arranged in the first bonding material layer;
epitaxially growing a whole layer of semiconductor buffer material layer, a whole layer of first semiconductor material layer, a whole layer of quantum well material layer and a whole layer of second semiconductor material layer on a wafer, so as to form an LED epitaxial layer;
depositing a whole layer of second bonding material layer on the second semiconductor material layer;
performing a bonding process on the whole layer of second bonding material layer and the reflective bonding structures arranged in the array.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
September 30, 2026
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