DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/02/2024 and 05/30/2025 are being considered by the examiner.
Drawings
The drawings submitted on 10/02/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are the “lower” friction coefficient compared to the other friction coefficient i.e. “a sheet including a surface with a coefficient of friction lower than a coefficient of friction of at least a part of a surface of the pressing member”. Additionally, what is the significance of these respective friction coefficients?
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa et al. (US 20050017373 A1) in view of Taniguchi et al. (WO 2007123199 A1).
Regarding claim 1, Nishikawa discloses an electrical circuit formation method comprising:
a fluid application step (Fig. 1A) of applying a conductive fluid (3) to a planned mounting position of an electrode (34) of an electronic component (30) on a metal wiring line (2) formed on a resin layer (1); ([0035], Fig. 1A)
a mounting step (Fig. 1C) of mounting the electronic component (30) such that the electrode (34) comes into contact with the conductive fluid (3); ([0035]-[0038], Fig. 1A-1C) and
Nishikawa does not explicitly disclose:
a pressing step of pressing the electronic component mounted in the mounting step relative to the resin layer by a pressing member in a state in which a sheet including a surface with a coefficient of friction lower than a coefficient of friction of at least a part of a surface of the pressing member that faces the electronic component is sandwiched between the electronic component and the pressing member.
However, Taniguchi discloses:
a pressing step (Fig. 5-6) of pressing the electronic component (40) mounted in the mounting step (Fig. 4) relative to the resin layer (31) by a pressing member (22) in a state in which a sheet (39) including a surface with a coefficient of friction (0.05-0.2 for Polytetrafluoroethylene per [0067]) lower than a coefficient of friction (rubber per [0020]) of at least a part of a surface of the pressing member (22) that faces the electronic component (40) is sandwiched between the electronic component (40) and the pressing member (22). ([0034], Fig. 6)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Nishikawa and Taniguchi to have a pressing step of pressing the electronic component mounted in the mounting step relative to the resin layer by a pressing member in a state in which a sheet including a surface with a coefficient of friction lower than a coefficient of friction of at least a part of a surface of the pressing member that faces the electronic component is sandwiched between the electronic component and the pressing member so that “the electrical components 40 and 45 are not displaced during pressing, and no voids are generated in the fillet portion. Therefore, the connection reliability of the electrical device 2 is high.” (Taniguchi, [0045])
Regarding claim 3, Nishikawa discloses the electrical circuit formation method according to claim 1, further comprising:
a resin application step (Fig. 1B) of applying a curable resin (6) onto the resin layer (1) to come into contact with a component body (32) of the electronic component (30), the resin application step (Fig. 1B) being provided before the pressing step (Fig. 1D). ([0037], [0051], Fig. 1B and 1D)
Regarding claim 5, Nishikawa discloses the electrical circuit formation method according to claim 1, further comprising: a curing step (per [0054]) of curing the conductive fluid (3) applied in the fluid application step. (Fig. 1A-1B)
Regarding claim 6, Nishikawa discloses an electrical circuit formation device comprising:
an application device configured to apply a conductive fluid (3) to a planned mounting position of an electrode (34) of an electronic component (30) on a metal wiring line (2) formed on a resin layer (1); ([0035], Fig. 1A)
a mounting device configured to mount (per [0038]) the electronic component (30) such that the electrode (34) comes into contact with the conductive fluid (3);
Nishikawa does not disclose:
and a pressing device configured to press the electronic component mounted by the mounting device relative to the resin layer by a pressing member in a state in which a sheet including a surface with a coefficient of friction lower than a coefficient of friction of at least a part of a surface of the pressing member that faces the electronic component is sandwiched between the electronic component and the pressing member.
However, Taniguchi discloses:
and a pressing device (10) configured to press the electronic component (40) mounted by the mounting device (26) relative to the resin layer (31) by a pressing member (22) in a state in which a sheet (39) including a surface with a coefficient of friction (0.05-0.2 for Polytetrafluoroethylene per [0067]) lower than a coefficient of friction (rubber per [0020]) of at least a part of a surface of the pressing member (22) that faces the electronic component (40) is sandwiched between the electronic component (40) and the pressing member (22). ([0034], Fig. 6)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Nishikawa and Taniguchi to have a pressing device configured to press the electronic component mounted by the mounting device relative to the resin layer by a pressing member in a state in which a sheet including a surface with a coefficient of friction lower than a coefficient of friction of at least a part of a surface of the pressing member that faces the electronic component is sandwiched between the electronic component and the pressing member so that “the electrical components 40 and 45 are not displaced during pressing, and no voids are generated in the fillet portion. Therefore, the connection reliability of the electrical device 2 is high.” (Taniguchi, [0045])
Claim 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa et al. (US 20050017373 A1) in view of Taniguchi et al. (WO 2007123199 A1) as applied to claim 1 above, and further in view of Tomura et al. (US 20110020983 A1).
Regarding claim 2, Nishikawa, in view of Taniguchi disclose the electrical circuit formation method according to claim 1. Nishikawa in view of Taniguchi do not disclose wherein in the pressing step, the electronic component mounted in the mounting step is pressed relative to the resin layer by the pressing member in a state in which a plurality of the sheets are stacked and sandwiched between the electronic component and the pressing member.
However, Tomura discloses:
in the pressing step (Fig. 3), the electronic component (1) mounted in the mounting step (Fig. 1) is pressed relative to the resin layer (6) by the pressing member (11) in a state in which a plurality of the sheets (10) are stacked and sandwiched between the electronic component (1) and the pressing member (11). ([0051]-[0056], Fig. 3)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Nishikawa, Taniguchi and Tomura to have in the pressing step, the electronic component mounted in the mounting step is pressed relative to the resin layer by the pressing member in a state in which a plurality of the sheets are stacked and sandwiched between the electronic component and the pressing member in order to have “a semiconductor device having high productivity and reliability can be produced in a short lead time” (Tomura, [0021])
Regarding claim 4, Tomura discloses the electrical circuit formation method according to claim 2, further comprising:
a resin application step (Fig. 1) of applying a curable resin (5) onto the resin layer (6) to come into contact with a component body (1) of the electronic component (1), the resin application step (Fig. 1) being provided before the pressing step (Fig. 3). ([0042]-[0054], Fig. 1-3)
It would have been obvious to one skilled in the art before ethe effective filing date to use the teachings of Tomura for similar reasons mentioned beforehand.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
