DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 306. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because the lower op-amp of Figure 3 is presented with positive feedback, rather than a negative feedback. It is suggested to review the polarity of the inputs to this op-amp and confirm desired positive feedback or make the correction to negative feedback by switching the input polarities. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
[0022] refers to “wrench body 104” instead of --wrench body 102--.
[0028] in the published document US20250283769A1, the equation reads as VS = Gain x Vzero = Vbias; however, it is noted that this should read, as indicated in the original specification, as --VS = Gain x Vzero + Vbias.
[0029] in the strict inequality (VREF - Vth) < VS < (VREF + Vth), if Vth = 0V, as suggested, this would be an impossible inequality. So, at best, Vth is required to be greater than 0V or the strict inequality can be modified to be less than or equal to.
[0030] in the published document US20250283769A1, the phrase reads “the bias voltage Vias of the differential”; however, it is noted that this should read, as indicated in the original specification, as --the bias voltage Vbias of the differential--.
[0034] refers to “ADC 308” instead of --ADC 306--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 20 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 20 is missing a dependency indication. It is assumed claim 20 is dependent upon claim 11, to match the similar claim construction of claim 10, which is dependent upon claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Anjanappa et al. (US 2011/0162493 A1) in view of Connolly et al. (US 2012/0105054 A1).
Considering claim 1, Anjanappa discloses an apparatus 10 for determining a torque value of an applied torque (Figure 4; [0032]), the apparatus comprising:
- a strain gauge assembly 33 (Figure 5; [0030]; [0033]) configured to measure the applied torque, and produce an analog electrical signal 60 that varies in voltage with the applied torque, the strain gauge assembly having a characteristic analog signal produced by the strain gauge assembly without any applied torque ([0032-33]);
- a differential voltage amplifier circuit (Figure 5, “Differential Voltage Amplifier”) configured to receive the analog electrical signal 60, and amplify the analog electrical signal to produce an amplified analog electrical signal 64 (Figure 5; [0033])
- an analog-to-digital converter (Figure 5; “Analog to Digital Converter” part of microcontroller 66) configured to convert the amplified analog electrical signal 64 to an equivalent digital electrical signal (“Digital Data Points”) (Figure 5; [0033]); and
- processing circuitry 66 (“Digital Filtering Algorithm and Calibration Formula”) configured to determine the torque value of the applied torque from the equivalent digital electrical signal (“Digital Data Points”) and output an indication 69 of the torque value (Figures 4-6; [0032-35]).
The invention by Anjanappa teaches that the microcontroller 66 samples the no-load voltage offset of the strain gage arrangement and biases the analog electrical signal 64 from the differential voltage amplifier to be zero at zero load, which therefore removes the characteristic analog signal. Anjanappa fails to explicitly disclose that the differential voltage amplifier circuit is biased to a bias voltage that is calibrated to reduce the characteristic voltage in the amplified analog electrical signal.
However, Connolly teaches the use of a strain gage bridge 124 connected to a differential voltage amplifier circuit 129 that is biased to a bias voltage that is calibrated to reduce the characteristic voltage in the amplified analog electrical signal (Figures 1-3; [0019]; [0022-28], whereby the amplified output 132, within the differential voltage amplifier circuit, is trimmed by the unloaded output error to a 2.5V level at zero-load, and trimming is maintained until a new zero-load error is requested).
One of ordinary skill in the art could have simply substituted the known differential amplifier biasing, taught by Connolly, for the microcontroller voltage offset technique used by Anjanappa, and the results of the substitution would have been predictable and repeatable. Both techniques are shown as providing no-load offset compensation and are thus considered functionally equivalent for providing this correction to an amplified signal. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a differential amplifier biasing technique, as suggested by Connolly, in the invention by Anjanappa.
Considering claim 10, Anjanappa discloses that the equivalent digital electrical signal includes digital data points, and the processing circuitry configured to determine the torque value includes the processing circuitry configured to (ADC-derived digital samples processed by microcontroller 66; [0033-34]):
- determine a subset of the digital data points in a moving sample window ([0034]); and
- calculate the torque value from a rolling average of the subset of the digital data points in the moving sample window ([0034-35], drops oldest, adds newest, re-averages and uses calibration formula for torque).
Considering claim 11, Anjanappa discloses a method of determining a torque value of an applied torque, the method comprising:
- measuring the applied torque using a strain gauge assembly 33 that produces an analog electrical signal 60 that varies in voltage with the applied torque, the strain gauge assembly having a characteristic analog signal produced by the strain gauge assembly without any applied torque (Figures 4-5; [0032-33]);
- receiving the analog electrical signal 60 at a differential voltage amplifier circuit (Figure 5, “Differential Voltage Amplifier”) that amplifies the analog electrical signal to produce an amplified analog electrical signal 64 (Figure 5; [0033]);
- converting the amplified analog electrical signal 64 to an equivalent digital electrical signal (Figure 5; “Digital Data Points”) using an analog-to-digital converter (Figure 5; “Analog to Digital Converter” part of microcontroller 66) (Figure 5; [0033]);
- determining the torque value of the applied torque from the equivalent digital electrical signal (Figures 4-6; [0032-35]); and
- outputting an indication of the torque value (Figures 4-6; [0032-35]).
The invention by Anjanappa teaches that the microcontroller 66 samples the no-load voltage offset of the strain gage arrangement and biases the analog electrical signal 64 from the differential voltage amplifier to be zero at zero load, which therefore removes the characteristic analog signal. Anjanappa fails to explicitly disclose that the differential voltage amplifier circuit is biased to a bias voltage that is calibrated to reduce the characteristic voltage in the amplified analog electrical signal.
However, Connolly teaches the use of a strain gage bridge 124 connected to a differential voltage amplifier circuit 129 that is biased to a bias voltage that is calibrated to reduce the characteristic voltage in the amplified analog electrical signal (Figures 1-3; [0019]; [0022-28], whereby the amplified output 132, within the differential voltage amplifier circuit, is trimmed by the unloaded output error to a 2.5V level at zero-load, and trimming is maintained until a new zero-load error is requested).
One of ordinary skill in the art could have simply substituted the known differential amplifier biasing, taught by Connolly, for the microcontroller voltage offset technique used by Anjanappa, and the results of the substitution would have been predictable and repeatable. Both techniques are shown as providing no-load offset compensation and are thus considered functionally equivalent for providing this correction to an amplified signal. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a differential amplifier biasing technique, as suggested by Connolly, in the invention by Anjanappa.
Considering claim 20, Anjanappa discloses that the equivalent digital electrical signal includes digital data points, and determining the torque value includes:
- determining a subset of the digital data points in a moving sample window ([0034]); and
- calculating the torque value from a rolling average of the subset of the digital data points in the moving sample window ([0034-35], drops oldest, adds newest, re-averages and uses calibration formula for torque).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Anjanappa et al. (US 2011/0162493 A1) in view of Connolly et al. (US 2012/0105054 A1), as applied to claims 1 and 11, respectively, above, and further in view of Distinti (US 5202687 A).
Considering claim 2, Anjanappa, as modified by Connolly, discloses using a VCC of 5V (Connolly, [0017]) to supply power to the components of the auto-zeroing circuitry and a 2.5V target no-load compensated output of a differential voltage amplifier ([0025]). It is noted that Connolly specifically presents a configuration where VREF becomes 2.5V when the VCC = 5V, through the voltage divider 118 ([0016]; [0022]), thus exemplifying the relationship of VREF = VCC/2.
The invention by Anjanappa, as modified by Connolly fails to disclose that the ADC has a reference voltage, and the bias voltage of the differential voltage amplifier circuit is calibrated such that the amplified analog electrical signal is within a threshold voltage of the reference voltage for the characteristic analog signal produced by the strain gauge assembly without any applied torque.
However, Distinti teaches the use of an analog-to-digital converter (SYMAD cells 12, Cell 1 to Cell(n)) having a reference voltage VREF that is equal to exactly half of the full scale input voltage of the system (Figure 3; Column 7, line 54 – Column 8, line 30).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a VREF, specifically that equals .5*VCC, with the ADC of Anjanappa, as modified by Connolly, as taught by Distiniti. The motivation for doing so is to allow measurement of torque difference signals in both directions, CCW and CW, as is understood in the art.
In combination, the bias voltage of the differential voltage amplifier circuit of Anjanappa, as modified by Connolly, is already set to be VREF = VCC/2, which is thus calibrated such that the amplified analog electrical signal is within a threshold voltage of the reference voltage of the ADC for the characteristic analog signal produced by the strain gauge assembly without any applied torque, because the VREF = VCC/2 of the ADC in Distiniti as well.
Considering claim 12, Anjanappa, as modified by Connolly, discloses using a VCC of 5V (Connolly, [0017]) to supply power to the components of the auto-zeroing circuitry and a 2.5V target no-load compensated output of a differential voltage amplifier ([0025]). It is noted that Connolly specifically presents a configuration where VREF becomes 2.5V when the VCC = 5V, through the voltage divider 118 ([0016]; [0022]), thus exemplifying the relationship of VREF = VCC/2.
The invention by Anjanappa, as modified by Connolly fails to disclose that the ADC has a reference voltage, and the bias voltage of the differential voltage amplifier circuit is calibrated such that the amplified analog electrical signal is within a threshold voltage of the reference voltage for the characteristic analog signal produced by the strain gauge assembly without any applied torque.
However, Distinti teaches the use of an analog-to-digital converter (SYMAD cells 12, Cell 1 to Cell(n)) having a reference voltage VREF that is equal to exactly half of the full scale input voltage of the system (Figure 3; Column 7, line 54 – Column 8, line 30).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a VREF, specifically that equals .5*VCC, with the ADC of Anjanappa, as modified by Connolly, as taught by Distiniti. The motivation for doing so is to allow measurement of torque difference signals in both directions, CCW and CW, as is understood in the art.
In combination, the bias voltage of the differential voltage amplifier circuit of Anjanappa, as modified by Connolly, is already set to be VREF = VCC/2, which is thus calibrated such that the amplified analog electrical signal is within a threshold voltage of the reference voltage of the ADC for the characteristic analog signal produced by the strain gauge assembly without any applied torque, because the VREF = VCC/2 of the ADC in Distiniti as well.
Claims 3-5 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Anjanappa et al. (US 2011/0162493 A1) in view of Connolly et al. (US 2012/0105054 A1), as applied to claims 1 and 11, respectively, above, and further in view of Distinti (US 5202687 A), as applied to claims 2 and 12, respectively above, and furthermore in view of Chau et al. (US 2012/0017696 A1).
Considering claim 3, the invention by Anjanappa, as modified by Connolly, discloses that the VCC is applied to the strain gauge assembly 124 through a temperature-correction circuit 128 including transistor Q1 and resistors R1 and R2 (Figure 2; [0017]). Further, Distinti already teaches that the reference voltage of the ADC is set to be half of the rail voltage. Accordingly, the combination fails to disclose that the excitation voltage is set to a rail voltage, whereby the reference voltage of the analog-to-digital converter is set to a proper fraction of the rail voltage and thereby the excitation voltage.
However, Chau teaches applying rail voltage (from 88) as the excitation voltage of a strain gauge assembly 82 (Figure 1; [0020-21]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to supply a direct rail voltage to the strain gauge assembly of the invention by Anjanappa, as modified by Connolly and Distinti, as taught by Chau. The motivation for doing so is to use a single regulated power source to supply power to all of the components, whereby the ratio of ADC reference voltage to excitation voltage remains fixed, reducing the relative drift between separate sources.
Considering claim 4, the invention by Anjanappa, as modified by Connolly and Distinti, has already established the at the Vbias of the differential voltage amplifier circuit is calibrated such that the amplified analog electrical signal is within the threshold voltage of VREF of the ADC, in claim 2, which according to claim 3, is a proper fraction of the excitation voltage. Thus, the combination already provides this relationship.
Considering claim 5, the invention by Anjanappa, as modified by Connolly and Distinti, has already established the VREF of the ADC equals VCC/2, which is one-half of the rail voltage VCC and thereby the excitation voltage, as already asserted in claims 2 and 3, above. Thus, the combination already provides this relationship.
Considering claim 13, the invention by Anjanappa, as modified by Connolly, discloses that the VCC is applied to the strain gauge assembly 124 through a temperature-correction circuit 128 including transistor Q1 and resistors R1 and R2 (Figure 2; [0017]). Further, Distinti already teaches that the reference voltage of the ADC is set to be half of the rail voltage. Accordingly, the combination fails to disclose that the excitation voltage is set to a rail voltage, whereby the reference voltage of the analog-to-digital converter is set to a proper fraction of the rail voltage and thereby the excitation voltage.
However, Chau teaches applying rail voltage (from 88) as the excitation voltage of a strain gauge assembly 82 (Figure 1; [0020-21]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to supply a direct rail voltage to the strain gauge assembly of the invention by Anjanappa, as modified by Connolly and Distinti, as taught by Chau. The motivation for doing so is to use a single regulated power source to supply power to all of the components, whereby the ratio of ADC reference voltage to excitation voltage remains fixed, reducing the relative drift between separate sources.
Considering claim 14, the invention by Anjanappa, as modified by Connolly and Distinti, has already established the at the Vbias of the differential voltage amplifier circuit is calibrated such that the amplified analog electrical signal is within the threshold voltage of VREF of the ADC, in claim 2, which according to claim 3, is a proper fraction of the excitation voltage. Thus, the combination already provides this relationship.
Considering claim 15, the invention by Anjanappa, as modified by Connolly and Distinti, has already established the VREF of the ADC equals VCC/2, which is one-half of the rail voltage VCC and thereby the excitation voltage, as already asserted in claims 2 and 3, above. Thus, the combination already provides this relationship.
Claims 6-9 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Anjanappa et al. (US 2011/0162493 A1) in view of Connolly et al. (US 2012/0105054 A1), as applied to claims 1 and 11, respectively, above, and further in view of Distinti (US 5202687 A), as applied to claims 2 and 12, respectively above, and furthermore in view of Kim (KR 10-2014-0006141 A).
Considering claim 6, the invention by Anjanappa, as modified by Connolly and Distinti, fails to disclose that the processing circuitry is further configured to calibrate the bias voltage to which the differential voltage amplifier circuit is biased, including the processing circuitry configured to at least determine a temporary bias voltage, bias the differential voltage amplifier circuit to the temporary bias voltage, as the characteristic analog electrical signal is applied to the differential voltage amplifier circuit to produce the amplified analog electrical signal, and set the bias voltage to the temporary bias voltage, responsive to the amplified analog electrical signal being within the threshold voltage of the reference voltage.
However, Kim teaches that the processing circuitry is further configured to calibrate the bias voltage to which the differential voltage amplifier circuit is biased, including the processing circuitry configured to at least:
- determine a temporary bias voltage ([0034]);
- bias the differential voltage amplifier circuit to the temporary bias voltage, as the characteristic analog electrical signal is applied to the differential voltage amplifier circuit to produce the amplified analog electrical signal ([0034-36]); and
- set the bias voltage to the temporary bias voltage, responsive to the amplified analog electrical signal being within the threshold voltage of the reference voltage ([0036-38]).
The invention by Anjanappa, as modified by Connolly, teaches a resettable one-shot compensation voltage based on a start-up bias offset. The invention by Kim suggests implementing an algorithm that provides a series of compensation bias voltages based on the continued offset fluctuations of the differential voltage amplifier, as compared to a fixed reference or range of values. One of ordinary skill in the art could have applied the known technique of Kim to the invention by Anjanappa, as modified by Connolly and Distinti, and arrived at the same claimed improvement of continual updates of the compensation bias voltage to correct the DC offset of the differential voltage amplifier. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the temporary differential voltage amplifier biasing process of Kim, in the invention by Anjanappa, as modified by Connolly and Distinti.
Considering claim 7, the invention by Anjanappa, as modified by Connolly and Distinti, discloses that the Vbias is set to 2.5V or VCC/2 and the VREF of the ADC is set to 2.5V or VCC/2, but fails to disclose determining the temporary bias voltage as the reference voltage of the analog-to-digital converter.
However, Kim teaches that the initial temporary bias voltage is set to VCC/2 ([0034]; [0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to determine the temporary bias voltage as the reference voltage of the analog-to-digital converter, as taught by Kim, in the invention by Anjanappa, as modified by Connolly and Distinti. The motivation for doing so is to set the desired output of the amplifier to its ideal condition of VCC/2, which is the VREF of the combination, as discussed in Kim ([0037]).
Considering claim 8, the invention by Anjanappa, as modified by Connolly and Distinti, fails to disclose processing circuitry configured to calibrate the bias voltage further includes the processing circuitry configured to determine an absolute difference between the reference voltage and the amplified analog electrical signal, and wherein the amplified analog electrical signal is within the threshold voltage of the reference voltage when the absolute difference is less than the threshold voltage.
However, Kim teaches comparing the corrected differential voltage amplifier output VL with a target reference voltage VR and/or a reference range until the output is within the reference range (Figure 2; [0048-55]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to compare an absolute difference between the reference voltage and the amplified analog electrical signal with a reference threshold, as taught by Kim, in the invention by Anjanappa, as modified by Connolly and Distinti. The motivation for doing so is to provide accurate results by repeatedly striving for the idealized output of the differential voltage amplifier, understood from the teachings of Kim.
Considering claim 9, the invention by Anjanappa, as modified by Connolly and Distinti, fails to disclose repeating the temporary bias voltage calibration.
However, Kim teaches that responsive to the amplified analog electrical signal not being within the threshold voltage of the reference voltage, the processing circuitry configured to calibrate the bias voltage further includes the processing circuitry configured to: adjust the temporary bias voltage; and bias the differential voltage amplifier circuit to the temporary bias voltage as adjusted, as the characteristic analog electrical signal is reapplied to the differential voltage amplifier circuit, wherein the processing circuitry is configured to adjust the temporary bias voltage, and bias the differential voltage amplifier circuit to the temporary bias voltage as adjusted, until the amplified analog electrical signal is within the threshold voltage of the reference voltage ([0048-58]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to iterate the process of Kim, in the invention by Anjanappa, as modified by Connolly and Distinti. The motivation for doing so is to provide accurate results by repeatedly striving for the idealized output of the differential voltage amplifier, understood from the teachings of Kim.
Considering claim 16, the invention by Anjanappa, as modified by Connolly and Distinti, fails to disclose calibrating the bias voltage to which the differential voltage amplifier circuit is biased, including at least: determining a temporary bias voltage; biasing the differential voltage amplifier circuit to the temporary bias voltage, as the characteristic analog electrical signal is applied to the differential voltage amplifier circuit to produce the amplified analog electrical signal; and setting the bias voltage to the temporary bias voltage, responsive to the amplified analog electrical signal being within the threshold voltage of the reference voltage
However, Kim teaches that calibrating the bias voltage to which the differential voltage amplifier circuit is biased, including at least:
- determining a temporary bias voltage ([0034]);
- biasing the differential voltage amplifier circuit to the temporary bias voltage, as the characteristic analog electrical signal is applied to the differential voltage amplifier circuit to produce the amplified analog electrical signal ([0034-36], no); and
- setting the bias voltage to the temporary bias voltage, responsive to the amplified analog electrical signal being within the threshold voltage of the reference voltage ([0036-38]).
The invention by Anjanappa, as modified by Connolly, teaches a resettable one-shot compensation voltage based on a start-up bias offset. The invention by Kim suggests implementing an algorithm that provides a series of compensation bias voltages based on the continued offset fluctuations of the differential voltage amplifier, as compared to a fixed reference or range of values. One of ordinary skill in the art could have applied the known technique of Kim to the invention by Anjanappa, as modified by Connolly and Distinti, and arrived at the same claimed improvement of continual updates of the compensation bias voltage to correct the DC offset of the differential voltage amplifier. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the temporary differential voltage amplifier biasing process of Kim, in the invention by Anjanappa, as modified by Connolly and Distinti.
Considering claim 17, the invention by Anjanappa, as modified by Connolly and Distinti, discloses that the Vbias is set to 2.5V or VCC/2 and the VREF of the ADC is set to 2.5V or VCC/2, but fails to disclose determining the temporary bias voltage as the reference voltage of the analog-to-digital converter.
However, Kim teaches that the initial temporary bias voltage is set to VCC/2 ([0034]; [0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to determine the temporary bias voltage as the reference voltage of the analog-to-digital converter, as taught by Kim, in the invention by Anjanappa, as modified by Connolly and Distinti. The motivation for doing so is to set the desired output of the amplifier to its ideal condition of VCC/2, which is the VREF of the combination, as discussed in Kim ([0037]).
Considering claim 18, the invention by Anjanappa, as modified by Connolly and Distinti, fails to disclose that calibrating the bias voltage further includes determining an absolute difference between the reference voltage and the amplified analog electrical signal, and wherein the amplified analog electrical signal is within the threshold voltage of the reference voltage when the absolute difference is less than the threshold voltage.
However, Kim teaches comparing the corrected differential voltage amplifier output VL with a target reference voltage VR and/or a reference range until the output is within the reference range (Figure 2; [0048-55]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to compare an absolute difference between the reference voltage and the amplified analog electrical signal with a reference threshold, as taught by Kim, in the invention by Anjanappa, as modified by Connolly and Distinti. The motivation for doing so is to provide accurate results by repeatedly striving for the idealized output of the differential voltage amplifier, understood from the teachings of Kim.
Considering claim 19, the invention by Anjanappa, as modified by Connolly and Distinti, fails to disclose repeating the temporary bias voltage calibration.
However, Kim teaches that responsive to the amplified analog electrical signal not being within the threshold voltage of the reference voltage, calibrating the bias voltage further includes: adjusting the temporary bias voltage; and biasing the differential voltage amplifier circuit to the temporary bias voltage as adjusted, as the characteristic analog electrical signal is reapplied to the differential voltage amplifier circuit, wherein the temporary bias voltage is adjusted, and the differential voltage amplifier circuit biased to the temporary bias voltage as adjusted, until the amplified analog electrical signal is within the threshold voltage of the reference voltage ([0048-58]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to iterate the process of Kim, in the invention by Anjanappa, as modified by Connolly and Distinti. The motivation for doing so is to provide accurate results by repeatedly striving for the idealized output of the differential voltage amplifier, understood from the teachings of Kim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN102638266A discloses supplying a Vref to an inverting input of a differential voltage amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jonathan M Dunlap whose telephone number is (571)270-1335. The examiner can normally be reached Mon-Fri 10AM - 7PM.
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/JONATHAN M DUNLAP/Primary Examiner, Art Unit 2855 September 19, 2026
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