Prosecution Insights
Last updated: October 01, 2026
Application No. 18/855,423

Method and Electronic Assembly for an Automation System

Non-Final OA §103
Filed
Oct 09, 2024
Priority
Apr 12, 2022 — EU 22167893 +1 more
Examiner
TRAN, VINCENT HUY
Art Unit
Tech Center
Assignee
Siemens Aktiengesellschaft
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
970 granted / 1120 resolved
+26.6% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
23 currently pending
Career history
1143
Total Applications
across all art units

Statute-Specific Performance

§101
8.4%
-31.6% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
26.5%
-13.5% vs TC avg
§112
10.5%
-29.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1120 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 11-24 are pending in the application. Examiner’s Note: The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/09/2024 was filed after the mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “control unit” in claim 1. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 11, 15-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loechner US Pub. No. 2005/0007077 in view of “Nature of power electronics and integration of power conversion with communication for talkative power” Xiangning He et al. (“He”). Loechner teaches an electronic assembly for automation system, the electronic assembly comprising [See fig. 1-2, 4-5, 7, 12; ¶2-6, 38-45]: an electronic channel or a plurality of electronic channels [120, 400, 700, and 1200]; and [0044] As explained above, digital communications may be transmitted the two-wire interface 108 simultaneously with the 4-20 mA control signal. Such communications may be transmitted/received by any of the controller 102, the field device 110, and the communicator 130. As described above, the 4-20 mA current is multiplied by a loop input voltage at the meeting of the two-wire interface with the interface circuit 120 of the field device 110 and provides electrical power to the field device, to thereby power, for example, the transducer 124 and the processor 122. at least one control unit [processor 122], an electronic channel or each electronic channel of the plurality of electronic channels comprising: a voltage input [202/204 of fig. 2, 502/504, 902/904] for applying an input voltage to the electronic channel [¶50, 59, 69]; [0050] In FIG. 2, interface circuit 200 has an input voltage U.sub.i across positive and negative terminals 202 and 204, respectively. Zener diodes 206 and 208 imply voltage regulation which takes some fraction of the input voltage U.sub.i and outputs this fraction as an output voltage U.sub.o, which is used to power circuitry including processor 122 and actuator 112. Excess output voltage is sinked to ground, as shown. The zener diodes 206 and 208 thus represent a power supply (and regulation) circuitry 210. a voltage output for tapping off an output voltage at the electronic channel [¶54-56. 62, 74; See fig. 2, 5…]; and a buck converter [408] which is configured to convert the input voltage applied to the voltage input to the output voltage which has a lower absolute value; [0055] An example of such a DC/DC converter 408 is discussed in commonly-assigned U.S. Pat. No. 6,064,583, which is hereby incorporated by reference. As described therein, such a DC/DC converter has a relationship between an input voltage U.sub.i and an output voltage U.sub.o such that (n x Uo) = Ui; e.g., for a 9V input, an output for n=3 would be 3V. The value "n" may be determined by a user for a particular application, based on available input voltages and DC/DC converters. Additionally, such a DC/DC converter 408 has the characteristic of bi-directional current flow; that is, current may flow from an input to an output of the DC/DC converter, or may flow from the output to the input of the DC/DC converter. Other DC/DC converters having similar characteristics could also be used. wherein the at least one control unit is configured to control the buck converter, including redirecting and modulating reverse current through the converter for transmitting digital communications over the two-wire loop [¶75-86] where the digital communication may employ the HART protocol [¶4-5, 52]. In other words, Loechner teaches using the buck converter as part of the communication path by modulating current through the converter. Loechner does not teach control the buck converter such that a signal in accordance with HART standard can be tapped off at a respective electronic channel via the output voltage. He teaches another integrating communication functionality directly into power electronic converters by controlling converter operation such that communication information is conveyed through the converter output while simultaneously performing voltage conversion. Specifically, He teaches a control unit is configured to control the buck converter such that a signal in accordance with digital communication standard can be tapped off at a respective electronic channel via the output voltage [See fig. 2 and 7 – Structure of a buck/boost converter]. PNG media_image1.png 567 524 media_image1.png Greyscale In this paper, we reconsider power electronic converters from an interdisciplinary perspective and propose a method of integrating communication into direct current (dc)–dc converters to achieve what we call ‘talkative power’. With the proposed integration method, it becomes possible for power to ‘talk’, or communicate, during conversion. The ‘talkative power’ converter has many applications in contexts such as distributed power electronic systems, modularized dc devices, luminaires and the Internet of Things, which are dual-purposed to provide both energy and communications currently in separate ways. In addition, a novel modulation method called frequency hopping–differential phase shift keying (FH-DPSK) is proposed along with the talkative power strategy to achieve effective communication while avoiding interference between power con-version and data transmission, which will be valuable for sup-porting new, advanced techniques in conventional light-emitting diode (LED)/lighting technology. Essential nature of power converters for communication. In a power electronic converter, a reference signal is modulated to a switching frequency to serve as the gate signal for one or more switches by a modulator and is then amplified by an input power source and the switch(es) (in some cases, passive elements are also involved). The modulated and amplified signal is then demodulated to obtain a signal with the required level of output power and the same form as the reference (usually either a dc form or a power frequency alternating current (ac) form). Accordingly, the power conversion process can be divided into distinct stages of modulation, power amplification and demodulation, which are, in some sense, analogous to the stages of the communication process. Transmission is ignored in this case since the modulator and demodulator are located at the same point in space. There are four kinds of power electronic converters, namely, dc–dc power converters, dc–ac inverters, ac–dc rectifiers and ac–ac power converters, among which dc–dc converters are the most basic. Various dc–dc topologies have been designed to meet different application requirements, such as buck converters for voltage step-down, boost converters for voltage step-up and buck–boost converters for inverse voltage step-up and step-down. [page 2] The buck/boost converter includes a power demodulator in the form of an LC LPF. Then the dc and residual switching frequency components are transferred to the load for power transfer and to the receiver(s) for data demodulation. Thus power and data modulation are combined, where the power signal is also the carrier of the data; as a result, power and data signals can be transmitted over a common power line. The load and receiver(s) can be integrated or separate, but they must be connected to the buck/boost output power line. Each receiver consists of a signal conditioning circuit to extract the switching frequency component for data demodulation. Under these conditions, data are embedded into and transmitted with the power signal; thus the output power signal can ‘talk’ to any device connected to the output power line, thereby achieving talkative power. [Read further page 4, 7-10] Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the converter of Loechner according to the teachings of He so that the HART communication signal generated by the converter is conveyed via the converter output voltage. Doing so would have predictably enabled the converter to simultaneously perform power conversion and communication while reducing circuit complexity, reducing component count, improving integration, improving power density, and simplifying the overall interface circuitry. Thus, reduce cost. Regarding claim 15, He teaches the output voltage has a value of between 8 volts and 25 volts [page 7 and 9 - the input voltage was set to 48 V, and the output voltage was 24 V]. Regarding claim 16, Loechner teaches the input voltage has a value of essentially 30 volts [¶38 – 24 V]. Regarding claim 17, He teaches the buck converter has at least one transistor [S1]; and wherein the control unit [modulator] is connected to a control input of the at least one transistor to control a switching state of the at least one transistor for converting the input voltage [See fig. 2]. Regarding claim 18, He teaches at least one transistor is a field effect transistor [See fig. 2 page 4 - MOSFET]. Regarding claim 19, Loechner teaches the electronic channel or the plurality of electronic channels each have an apparatus for detecting a value of a current through a respective electronic channel [¶52]. Regarding claim 20, Loechner teaches control unit is a Field Programmable Gate Array or a microcontroller [processor]. Regarding claim 21, Loechner teaches at least one processor unit [102] for operating and monitoring the technical installation and an electronic assembly connected to a computer unit as claimed in claim 11 [¶2-6; fig. 1]. Regarding claim 22, Loechner teaches the technical system comprises a production or process installation [¶2-6; fig. 1]. Regarding claim 23, it is directed to the method of steps to implement the system as set forth in claim 11. Therefore, it is rejected on the same basis as set forth hereinabove. Regarding claim 24, Loechner teaches the output voltage applied to the voltage output is utilized to operate a measuring device for detecting a physical variable [¶2, 4]. Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loechner/He as applied to claim 11 above, and further in view of Longsdorf et al. U.S. Patent No. 6,006,338 (“Longsdorf”). Regarding claim 12, Loechner in view He teaches controlling the buck converter to transmit digital/HART communication through the converter output power line but does not specify particular communication frequency. Loechner/He does not teach an oscillation frequency of the output voltage is in a range from 100 hertz to 3000 hertz. Longsdorf teaches that digital communication in industrial process control systems employing the HART protocol is transmitted using frequency-shift keying in which the information signal is represented by 1200 Hz and 2200 Hz frequencies superimposed on the analog process signal. The communications circuitry 42 is coupled to the power source 38, the modem 18 and link terminals 40 to transmit the process signal and the transmitter information signal onto the process link 12 according to selected communications protocols. The process signal is transmitted on the process link 12 by controlling the level of current through the process link 12 between 4-20 mA, for example. The information signal is shown as a modulated signal 48 on the current through the process link 12. Two of the communications protocols available for the process transmitter 10 to communicate the transmitter information signal 48 are the Highway Addressable Remote Transducer (HART.RTM.) communications protocol, which is described in HART.RTM. Field Communications Protocol, A Technical Overview (1994) available from the HART Communications Foundation in Austin, Tex. USA, and the Fieldbus communications protocols such as Foundation.TM. Fieldbus, Controller Area Network (CAN), Lonworks, and Profibus. Foundation Fieldbus is described in Understanding Fieldbus (1996) available from Rosemount Measurement in Eden Prairie, Minn., USA. With the HART communication protocol, the analog process signal generated by the communications circuitry 42 over the process link 12 is preferably a 4-20 mA DC analog signal, and the information signal 48 is a digital signal having a frequency of 1200 Hz and 2200 Hz at 1.0 mA peak-to-peak modulated on the analog process signal. In another form of the HART communications protocol, both the process signal and the transmitter signal are digital signals modulated on a substantially fixed current in the range from about 1-10 mA, preferably about 4 mA DC. With the Fieldbus communications protocol, both the process signal and the transmitter signal are digital signals modulated on a substantially fixed current in the range from about 4-20 mA DC and preferably about 16 mA DC. [Col. 4 lines 17-50] Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the converter-based communication system of Loechner/He such that an oscillation frequency of the output voltage is in a range from 100 hertz to 3000 hertz a well-known HART communication frequencies taught by Longsdorf. The motivation for doing so would have been pro provide compatibility and interoperability with existing HART compatible industrial automation equipment and field devices, since HART communication using Bell 202 FSK frequencies of 1200 Hz and 2200 Hz was a well-established industrial standard. Regarding claim 13, Loechner/He in view of Longsdorf teaches the oscillation frequency of the output voltage is a range from 1000 hertz to 2500 hertz. Regarding claim 14, He teaches the output voltage has a value of between 8 volts and 25volts [page 7 - the input voltage was set to 48 V, and the output voltage was 24 V]. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2018/0234263 to Wunderlich et al. teach a Field-device coupling unit for providing a supply voltage for a field device and for communication with a superordinate control unit, the field-device coupling unit including a current interface, which is configured for communication with the control unit and has a first controllable input load which is configured to provide, from an interface current of the current interface, a load voltage on which the supply voltage is based, the field-device coupling unit further including a circuit arrangement for providing a communication signal which is to be transmitted to the control unit, wherein the circuit arrangement is configured to control the first controllable input load according to the communication signal in order to superimpose the interface current with a current signal corresponding to the communication signal. US Pub. No. 2023/0292419 to Zeng et al. teach an monolithic integrated chip includes: a power conversion module, connected to a central processing unit, a communication module, an analog-to-digital conversion module, a resistor divider module and a drive module, for generating internal power supply and providing power to the central processing unit, the communication module, the analog-to-digital conversion module, the resistor divider module and the drive module; the central processing unit, connected to the communication module, the analog-to-digital conversion module, the resistor divider module and the drive module, for controlling signal transmission between a host and slaves; the communication module, connected to the bus voltage input pin, for transmitting signals between the host and the slaves; the analog-to-digital conversion module, connected to the resistor divider module, for converting an analog signal to a digital signal; the resistor divider module, connected to the first drive signal output pin, the second drive signal output pin, and the third drive signal output pin, for obtaining resistance division voltage values; the drive module, connected to the first drive signal output pin, the second drive signal output pin, and the third drive signal output pin, for driving the first light circuit, the second light circuit, and the third light circuit Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT HUY TRAN whose telephone number is (571)272-7210. The examiner can normally be reached M-F 7:00-4:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini S Shah can be reached at 571-272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. VINCENT H TRAN Primary Examiner Art Unit 2115 /VINCENT H TRAN/Primary Examiner, Art Unit 2115
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Prosecution Timeline

Oct 09, 2024
Application Filed
Apr 30, 2025
Response after Non-Final Action
Sep 24, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+9.7%)
2y 7m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1120 resolved cases by this examiner. Grant probability derived from career allowance rate.

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