/DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 11 is objected to because of the following informalities: It appears the long and short “sizes” of the rectangular shapes should be “sides”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7, 8, 10, and11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US 2019/0035154 A1).
Claim 1, Liu teaches an image sensor (sensor assembly 300; Fig. 3) comprising:
a layered structure (stacked structure of Fig. 3) that includes
a first layer that includes a pixel array unit where multiple pixels are two-dimensionally arrayed (photodetector layer 305 may comprise a two-dimensional array of photodiodes; paragraph 0038),
a second layer that includes a conversion processing unit configured to perform A/D conversion for converting an analog signal based on a pixel signal output from the pixel array unit, into a digital signal (ADC layer 315 is customized for conversion of analog signals into digital data; paragraph 0038), and a second layer storage unit configured to store image data for each frame, the image data being digital data based on the digital signal (ADC layer 315 may also include a memory for storing the digital values; paragraph 0038), and
a third layer (a layer comprising feature extraction layer 320 and convolution neural network CNN layer 325; paragraph 0040 and Fig. 3) that includes an inference processing unit configured to perform an inference process (CNN layer 325 is designed to perform image classification and recognition applications; see paragraph 0041) on a basis of the image data as an input tensor (CNN layer 325 applies weights to an input image from ADC layer; see paragraph 0041).
Claim 2, Liu further teaches wherein the second layer is provided between the first layer and the third layer (see Fig. 3).
Claim 3, Liu further teaches wherein a third layer storage unit designated as a working memory for the inference process is provided in the third layer (neural network 500 can be employed as a memory storage device and as a computational device; paragraph 0054).
Claim 5, Liu further teaches wherein a processor different from a processor functioning as the inference processing unit is provided in the third layer (feature extraction circuitry; paragraph 0039 and Fig. 3).
Claim 7, Liu further teaches wherein a communication control unit that performs communication control for outputting a result of the inference process to an outside is provided in the third layer (CNN layer 325 inherently comprises a communication unit to communicate, i.e., output, image classification and recognition information to a shared bus to provide a scalable network of sensor devices 130; paragraph 0022).
Claim 8, Liu further teaches wherein the first layer, the second layer, and the third layer have an identical chip size (see Fig. 2).
Claim 10, Liu further teaches wherein multiple chips are provided in the third layer (feature extraction layer 320 and CNN layer 325; Fig. 3).
Claim 11, Liu further teaches wherein each of the multiple chips has a rectangular shape having long sizes and short sizes in a planar view (see rectangular shape of each layer in Fig. 2), and the multiple chips are provided such that the long sizes face each other (the layers are stacked such that the long sides are aligned with one another, see Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 9, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu Liu (US 2019/0035154 A1).
Claim 4, Liu teaches the image sensor according to claim 1, but is silent regarding wherein the conversion processing unit and the inference processing unit are disposed at positions not overlapping each other in a lamination direction of the respective layers.
However, Liu describes a stacked sensor architecture with separate layers for analog-to-digital conversion and for inference processing (paragraph 0036-0041). Liu is silent regarding any specific positioning of these functional blocks in the lamination direction, but it would have been an obvious matter of design choice to a person having ordinary skill in the art before the effective filing date of the claimed invention arrange the ADC and inference layers at non-overlapping positions in the stack to minimize interference or to optimize layout as such spatial separation is a routine layout consideration in 3D ICs and mixed-signal systems, especially where analog and digital functions are integrated. The selection of overlapping or non-overlapping locations is a matter of predictable engineering optimization.
Claim 9, Liu teaches the image sensor according to claim 1, but is silent regarding wherein the third layer has a smaller chip size than the first layer and the second layer.
However, Liu teaches that different layers in the stack may be fabricated using different process technologies and may have different functional area requirements (paragraph 0037, 0041). For example, the CNN layer can be implemented in a smaller area than the pixel array or ADC, depending on transistor density and required logic. It would have been an obvious matter or design choice to a person having ordinary skill in the art before the effective filing date of the claimed invention to make the third (processing/inference) layer smaller than the sensor or ADC layers to reduce cost, improve yield, or match the functional area, as is standard in stacked die and sensor manufacturing. Liu’s discussion of wafer scaling and post-stacking dicing (paragraph 0046) further supports that die sizes can be optimized independently.
Claim 12, Liu teaches the image sensor according to claim 1, and further teaches wherein inference processing is performed after A/D conversion (paragraph 0044), but is silent regarding wherein overlap in execution timing between the A/D conversion in the second layer and the inference process in the third layer is prevented.
However, preventing simultaneous operation of A/D conversion and digital inference to avoid interference or noise is a well-known technique in mixed-signal system design. It would have been an obvious matter of design choice to a person having ordinary skill in the art before the effective filing date of the claimed invention to schedule A/D conversion and inference operations sequentially, rather than concurrently, to minimize noise coupling and ensure data integrity, as is standard practice in the art when integrating analog and digital circuits in proximity.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu Liu (US 2019/0035154 A1) in view of Wang (US 2024/0388444 A1).
Claim 6, Liu teaches the image sensor according to claim 1, but is silent regarding wherein an authentication processing unit that performs an authentication process for permitting or prohibiting deployment of an artificial intelligence model to be used for the inference process is provided in the third layer.
Wang teaches an authentication processing unit (neutral network unit; paragraph 0028) that performs an authentication process for permitting or prohibiting deployment of an artificial intelligence model to be used for the inference process (verifier data is used to prevent unauthorized access to the AI model; see paragraph 0127).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the teaching of Wang with that of Liu in order to protect a neural network to “ensure trustworthiness of the indication of ownership of the model as well as the integrity of the content of the model,” see paragraph 0007 of Wang.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 attached.
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/CHIAWEI CHEN/Primary Examiner, Art Unit 2637