DETAILED ACTION
This Office Action is in response to the Application filed 10 October 2024. Claims 1-7 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “region width of the plurality of fourth semiconductor regions of the first active region along an extending direction of the gate electrode is formed to be shorter than the region width of the plurality of fourth semiconductor regions of the second active region” from Claim 4 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 4, Claim 4 claims “a region width of the plurality of fourth semiconductor regions of the first active region along an extending direction of the gate electrode is formed to be shorter than the region width of the plurality of fourth semiconductor regions of the second active region”. This is unclear because “the extending direction of the gate electrode” can interpreted 2 ways, and it is unclear which the claim refers to. The extending direction of the gate electrode can either mean the direction the gate extends into the body and base layers (vertical direction), or the extending direction of the orthographic projection (a horizontal direction). For purposes of examination, the claim will be treated as referring the extending direction of the orthographic projection. In order to conform with applicant’s disclosure as shown in Fig. 5 (on which claim 4 is based) which shows no difference in the extension in the vertical direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuda et. al (US 2017/0179108 A1).
Regarding Claim 1, Okuda discloses (as shown in Fig. 17-19A, 21) A power semiconductor device ([0046] The semiconductor device 11 according to this embodiment is constituted by a power MOSFET or IGBT) in which a main current flows in a thickness direction of a semiconductor substrate ([0130] With reference to FIGS. 19A and 19B, the previously described substrate 2 includes an n+ type semiconductor substrate 20 and an n- type epitaxial layer 55 formed on the semiconductor substrate 20), (See Fig. 19a, showing the drain metal 57 on the bottom of the substrate 2 and the source metal 10 above of the substrate 2)
the semiconductor substrate (2) including: a first active region ([0115] a unit U1) provided in a central portion of the semiconductor substrate (2) and through which the main current flows; ([0115] With reference to FIG. 17, the plurality of functional element forming regions 14 includes a unit U1 of first functional element forming regions including a plurality of (four in this embodiment) first functional element forming regions 15)
and a second active region ([0115] a third unit U3) provided outside the first active region (U1), (Se Fig. 17, showing the third unit U3 surrounds the first unit U1)
the power semiconductor device comprising: a first main electrode ([0131] source metal 10) provided on the first (U1) and second (U3) active regions; ([0131] The previously described source metal 10 is formed on the surface side of the substrate 2)
and a second main electrode ([0131] drain metal 57) provided on a main surface of the semiconductor substrate (2) opposite to the first main electrode (10), ([0131] the drain metal 57 is formed on the rear surface side of the substrate 2. The drain metal 57 may correspond to the previously described the first electrode 112a)
wherein the second active region (U3) has first two sides facing each other in a first direction and second two sides facing each other in a second direction orthogonal to the first direction, (See Fig. 17, showing the third unit U3 has a rectangular shape)
a distance of the first active region (U1) from a center of the semiconductor substrate is set to less than 1/4 of a shorter length of a first length between the first two sides of the second active region (U2) or a second length between the second two sides of the second active region (U2) in a case where the first length and the second length are different, and is set to less than 1/4 of either length in a case where the first length and the second length have no difference, (See Fig. 21, showing that each subarea U3 is equal to the area of U1. Fig. 21 further shows 3 subareas U3 surround the area U1 on either side. Therefore, the length of either side is equal to 3 times the length of the area U3 or 6 times half the length of U3.)
and a first conduction capability of the first active region is set lower than a second conduction capability of the second active region. ([0121] With reference to FIG. 18A, the unit U1 of first functional element forming regions includes a plurality of first functional element forming regions 15 with the area ratio of the channel forming region 13 per unit area set to approximately 25%... With reference to FIG. 18C, the unit U3 of third functional element forming regions includes a plurality of third functional element forming regions 17 with the area ratio of the channel forming region 13 per unit area set to approximately 50%.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application that the unit U1 would have a lower conduction capacity than the unit U3 since the channel forming region is a smaller portion of the area. ([0121] With reference to FIG. 18A, the unit U1 of first functional element forming regions includes a plurality of first functional element forming regions 15 with the area ratio of the channel forming region 13 per unit area set to approximately 25%... With reference to FIG. 18C, the unit U3 of third functional element forming regions includes a plurality of third functional element forming regions 17 with the area ratio of the channel forming region 13 per unit area set to approximately 50%.)
Claim(s) 2, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuda as applied to claim 1 above, and further in view of Ukegawa (JP 2019212809 A).
Regarding Claim 2, Okuda fails to disclose a conductor plate directly bonded to the first main electrode via a first bonding layer; and a heat dissipation plate directly bonded to the second main electrode via a second bonding layer.
Ukegawa discloses (as shown in Fig. 2) a conductor plate (([0012] The upper heat sink 22 has … a first inner conductor layer 26) directly bonded to the first main electrode ([0012] surface electrode 20a of the first semiconductor element 20) via a first bonding layer ([0012] the solder layer 42); ([0012] The upper heat sink 22 has an insulating substrate 28, a first inner conductor layer 26, a second inner conductor layer 27, and an outer conductor layer 30. The first inner conductor layer 26 is located on one side of the insulating substrate 28 and is electrically connected to the surface electrode 20a of the first semiconductor element 20 via the solder layer 42)
and a heat dissipation plate ([0013] The lower heat sink 24 has … a first inner conductor layer 32) directly bonded to the second main electrode ([0013] the back electrode 20b of the first semiconductor element 20) via a second bonding layer ([0013] the solder layer 44). ([0013] The first inner conductor layer 32 is located on one side of the insulating substrate 34 and is electrically connected to the back electrode 20b of the first semiconductor element 20 via the solder layer 44)
Ukegawa teaches that the upper and lower heat sinks release the heat of the semiconductor device to the outside. ([0015] Thus, the upper heat sink 22 functions not only as a part of the semiconductor device 10 but also as a heat sink for releasing the heat of the first semiconductor element 20 and the second semiconductor element 40 to the outside… Accordingly, the lower heat sink 24 not only constitutes a part of the electric circuit of the semiconductor device 10 but also functions as a heat sink for releasing the heat of the first semiconductor element 20 and the second semiconductor element 40 to the outside.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the upper and lower heat sinks of Ukegawa with the semiconductor device of Okuda in order to release heat to the outside.
Regarding Claim 7, Okuda further discloses (as shown in Fig. 12, 19a) wherein the second main electrode (57) is provided over the entire main surface of the semiconductor substrate (2), (See Fig. 4, showing the first electrode 112a across the entire backside of the semiconductor device 11) ([0131] The previously described source metal 10 is formed on the surface side of the substrate 2, and the drain metal 57 is formed on the rear surface side of the substrate 2. The drain metal 57 may correspond to the previously described the first electrode 112a.)
Ukegawa further discloses (as shown in Fig. 2) the second bonding layer (44) is provided over an entire main surface of the second main electrode (20b). (See Fig. 2)
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuda as applied to claim 1 above, and further in view of Yamaguchi (US 2012/0025263 A1).
Regarding Claim 3, Okuda further discloses (as shown in Fig. 19a) a first semiconductor region of a first conductivity type ([0130] With reference to FIGS. 19A and 19B, the previously described substrate 2 includes an n+ type semiconductor substrate 20 and an n- type epitaxial layer 55 formed on the semiconductor substrate 20.) provided on the second main electrode; ([0131] the drain metal 57 is formed on the rear surface side of the substrate 2)
a second semiconductor region of a second conductivity type ([0133] a p type body region 28) provided on the first semiconductor region (2); (See Fig. 19A)
a plurality of third semiconductor regions of a first conductivity type selectively ([0133] An n+ type source region 27) provided on an upper layer portion of the second semiconductor region (28);
a plurality of trenches ([0131] trench 24) penetrating the second semiconductor region (28) and reaching the first semiconductor region (2); (See fig. 19A, showing the gate trenches 24 pass through the body region 28 into the substrate 2)
a gate insulating film ([0131] gate insulating film 25) provided on an inner wall of each of the plurality of trenches (24); and a gate electrode ([0131] gate electrode 26) filled inside each of the gate insulating films (25), ([0131] The previously described trench gate structures 54 are made in the surface part of the epitaxial layer 55, and includes the trench 24 dug through the epitaxial layer 55 and the gate electrode 26 embedded in the trench 24 with the gate insulating film 25 sandwiched therebetween.)
one side surface of each of the plurality of third semiconductor regions (27) is provided so as to be in contact with a side surface of each of the plurality of trenches (24) (See Fig. 19A)
However, Okuda fails to disclose wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type provided on the second main electrode;
a second semiconductor region of a first conductivity type provided on the first semiconductor region;
a third semiconductor region of a second conductivity type provided on the second semiconductor region;
a plurality of fourth semiconductor regions of a first conductivity type selectively provided on an upper layer portion of the third semiconductor region;
a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region;
a gate insulating film provided on an inner wall of each of the plurality of trenches;
and a gate electrode filled inside each of the gate insulating films,
one side surface of each of the plurality of fourth semiconductor regions is provided so as to be in contact with a side surface of each of the plurality of trenches,
and an impurity concentration of the plurality of fourth semiconductor regions in the first active region is set to be lower than an impurity concentration of the plurality of fourth semiconductor regions in the second active region.
Yamaguchi discloses (as shown in Fig. 6, 12) wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type ([0086] p+ collector region 2) provided on the second main electrode ([0085] collector electrode 12); (See Fig. 12)
a second semiconductor region ([0086] n- epitaxial region 4 … n+ epitaxial region 3) of a first conductivity type provided on the first semiconductor region (2); ([0086] n- epitaxial region 4 is formed on p+ collector region 2 with n+ epitaxial region 3 therebetween)
a third semiconductor region ([0087] p-type base region 5) of a second conductivity type provided on the second semiconductor region (3,4); (See Fig. 12)
a plurality of fourth semiconductor regions of a first conductivity type ([0085] an n+ emitter region 6) selectively provided on an upper layer portion of the third semiconductor region (5); (See Fig. 12, showing 2 emitter regions 6 on each base region 5)
a plurality of trenches ([0138] trench 1a) penetrating the third semiconductor region (5) and reaching the second semiconductor region (3,4); (See Fig. 12, showing the trench 1a passes through the base region 5 into the n- epitaxial region 4)
a gate insulating film ([0138] gate insulating film 8) provided on an inner wall of each of the plurality of trenches (1a); and a gate electrode ([0138] gate electrode layer 9) filled inside each of the gate insulating films (8), ([0138] that gate electrode layer 9 fills a trench 1a formed at the main surface of semiconductor substrate 1 with gate insulating film 8 interposed therebetween)
one side surface of each of the plurality of fourth semiconductor regions (6) is provided so as to be in contact with a side surface of each of the plurality of trenches (1a), (See Fig. 12)
and an impurity concentration of the plurality of fourth semiconductor regions (6) in the first active region ([0107] central portion CR) is set to be lower than an impurity concentration of the plurality of fourth semiconductor regions (6) in the second active region ([0107] outer peripheral portion PR). ([0107] More specifically, the n-type impurity concentration of n+ emitter region 6 is lower in the cell structure of central portion CR than that in outer peripheral portion PR.)
Okuda teaches that the semiconductor device can be a MOSFET or IGBT. ([0046] The semiconductor device 11 according to this embodiment is constituted by a power MOSFET or IGBT.) However, Okuda only discloses the structure of a vertical MOSFET. Yamaguchi discloses the structure of a vertical IGBT. Therefore,, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the structure of the IGBT as disclosed in Yamaguchi to make the IGBT version of the device in Okuda.
Furthermore, Yamaguchi teaches that lowering the current carrying capacity of the central portion lowers the heating value of the central portion, thereby making the joint temperature uniform and increasing power cycle life. ([0112] However, according to the embodiment, the cell structure in central portion CR has a lower current carrying ability than that in outer peripheral portion PR. Therefore, a heating value in the cell structure of central portion CR can be smaller than that in the outer peripheral portion. Thereby, joint temperature Tj can be uniform in central portion CR and outer peripheral portion PR, and maximum joint temperature Tjmax. in the chip can be low. Accordingly, .DELTA.Tj can be small and the power cycle life can be improved.) Yamaguchi further teaches that this can be achieved by changing the concentration of the emitter region 6. ([0107] The diffusion resistance of n+ emitter region 6 can be changed by changing the n-type impurity concentration of n+ emitter region 6. More specifically, the n-type impurity concentration of n+ emitter region 6 is lower in the cell structure of central portion CR than that in outer peripheral portion PR.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the different concentration of emitter regions in Yamaguchi with the device in Okuda in order to increase the power life cycle.
Regarding Claim 4, Okuda further discloses (as shown in Fig. 19a) a first semiconductor region of a first conductivity type ([0130] With reference to FIGS. 19A and 19B, the previously described substrate 2 includes an n+ type semiconductor substrate 20 and an n- type epitaxial layer 55 formed on the semiconductor substrate 20.) provided on the second main electrode; ([0131] the drain metal 57 is formed on the rear surface side of the substrate 2)
a second semiconductor region of a second conductivity type ([0133] a p type body region 28) provided on the first semiconductor region (2); (See Fig. 19A)
a plurality of third semiconductor regions of a first conductivity type selectively ([0133] An n+ type source region 27) provided on an upper layer portion of the second semiconductor region (28);
a plurality of trenches ([0131] trench 24) penetrating the second semiconductor region (28) and reaching the first semiconductor region (2); (See fig. 19A, showing the gate trenches 24 pass through the body region 28 into the substrate 2)
a gate insulating film ([0131] gate insulating film 25) provided on an inner wall of each of the plurality of trenches (24); and a gate electrode ([0131] gate electrode 26) filled inside each of the gate insulating films (25), ([0131] The previously described trench gate structures 54 are made in the surface part of the epitaxial layer 55, and includes the trench 24 dug through the epitaxial layer 55 and the gate electrode 26 embedded in the trench 24 with the gate insulating film 25 sandwiched therebetween.)
one side surface of each of the plurality of third semiconductor regions (27) is provided so as to be in contact with a side surface of each of the plurality of trenches (24) (See Fig. 19A)
a region width of the plurality of third semiconductor regions (27) of the first active region (U1) along an extending direction of the gate electrode (26) is formed to be shorter than the region width of the plurality of third semiconductor regions (27) of the second active region (U3). ([0121] With reference to FIG. 18A, the unit U1 of first functional element forming regions includes a plurality of first functional element forming regions 15 with the area ratio of the channel forming region 13 per unit area set to approximately 25%... With reference to FIG. 18C, the unit U3 of third functional element forming regions includes a plurality of third functional element forming regions 17 with the area ratio of the channel forming region 13 per unit area set to approximately 50%.) (See Figs. 18A,C)
However, Okuda fails to disclose wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type provided on the second main electrode;
a second semiconductor region of a first conductivity type provided on the first semiconductor region;
a third semiconductor region of a second conductivity type provided on the second semiconductor region;
a plurality of fourth semiconductor regions of a first conductivity type selectively provided on an upper layer portion of the third semiconductor region;
a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region;
a gate insulating film provided on an inner wall of each of the plurality of trenches;
and a gate electrode filled inside each of the gate insulating films,
one side surface of each of the plurality of fourth semiconductor regions is provided so as to be in contact with a side surface of each of the plurality of trenches,
Yamaguchi discloses (as shown in Fig. 6, 12) wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type ([0086] p+ collector region 2) provided on the second main electrode ([0085] collector electrode 12); (See Fig. 12)
a second semiconductor region ([0086] n- epitaxial region 4 … n+ epitaxial region 3) of a first conductivity type provided on the first semiconductor region (2); ([0086] n- epitaxial region 4 is formed on p+ collector region 2 with n+ epitaxial region 3 therebetween)
a third semiconductor region ([0087] p-type base region 5) of a second conductivity type provided on the second semiconductor region (3,4); (See Fig. 12)
a plurality of fourth semiconductor regions of a first conductivity type ([0085] an n+ emitter region 6) selectively provided on an upper layer portion of the third semiconductor region (5); (See Fig. 12, showing 2 emitter regions 6 on each base region 5)
a plurality of trenches ([0138] trench 1a) penetrating the third semiconductor region (5) and reaching the second semiconductor region (3,4); (See Fig. 12, showing the trench 1a passes through the base region 5 into the n- epitaxial region 4)
a gate insulating film ([0138] gate insulating film 8) provided on an inner wall of each of the plurality of trenches (1a); and a gate electrode ([0138] gate electrode layer 9) filled inside each of the gate insulating films (8), ([0138] that gate electrode layer 9 fills a trench 1a formed at the main surface of semiconductor substrate 1 with gate insulating film 8 interposed therebetween)
one side surface of each of the plurality of fourth semiconductor regions (6) is provided so as to be in contact with a side surface of each of the plurality of trenches (1a), (See Fig. 12)
Okuda teaches that the semiconductor device can be a MOSFET or IGBT. ([0046] The semiconductor device 11 according to this embodiment is constituted by a power MOSFET or IGBT.) However, Okuda only discloses the structure of a vertical MOSFET. Yamaguchi discloses the structure of a vertical IGBT. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the structure of the IGBT as disclosed in Yamaguchi to make the IGBT version of the device in Okuda.
Furthermore, Okuda teaches that the source region 27 corresponds to the emitter region of the IGBT. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the fourth semiconductor regions ([0085] an n+ emitter region 6) of the IGBT of Okuda in view of Yamaguchi have a region width of the plurality of fourth semiconductor regions of the first active region along an extending direction of the gate electrode is formed to be shorter than the region width of the plurality of fourth semiconductor regions of the second active region like the source regions in the vertical MOSFET of Okuda in order to suppress the heat generation in the central region. ([0010] The plurality of functional element forming regions includes a first functional element forming region in which the area of the channel forming region per unit area is relatively small and a second functional element forming region in which the area of the channel forming region per unit area is relatively large. With this configuration, the first functional element forming region is provided at the region where heat generation should be suppressed.)
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuda as applied to claim 1 above, and further in view of Yamaguchi (US 2012/0025263 A1) and Kanamaru (JP 2004363327 A).
Regarding Claim 5, Okuda further discloses (as shown in Fig. 19a) a first semiconductor region of a first conductivity type ([0130] With reference to FIGS. 19A and 19B, the previously described substrate 2 includes an n+ type semiconductor substrate 20 and an n- type epitaxial layer 55 formed on the semiconductor substrate 20.) provided on the second main electrode; ([0131] the drain metal 57 is formed on the rear surface side of the substrate 2)
a second semiconductor region of a second conductivity type ([0133] a p type body region 28) provided on the first semiconductor region (2); (See Fig. 19A)
a plurality of third semiconductor regions of a first conductivity type selectively ([0133] An n+ type source region 27) provided on an upper layer portion of the second semiconductor region (28);
a plurality of trenches ([0131] trench 24) penetrating the second semiconductor region (28) and reaching the first semiconductor region (2); (See fig. 19A, showing the gate trenches 24 pass through the body region 28 into the substrate 2)
a gate insulating film ([0131] gate insulating film 25) provided on an inner wall of each of the plurality of trenches (24); and a gate electrode ([0131] gate electrode 26) filled inside each of the gate insulating films (25), ([0131] The previously described trench gate structures 54 are made in the surface part of the epitaxial layer 55, and includes the trench 24 dug through the epitaxial layer 55 and the gate electrode 26 embedded in the trench 24 with the gate insulating film 25 sandwiched therebetween.)
one side surface of each of the plurality of third semiconductor regions (27) is provided so as to be in contact with a side surface of each of the plurality of trenches (24) (See Fig. 19A)
However, Okuda fails to disclose wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type provided on the second main electrode;
a second semiconductor region of a first conductivity type provided on the first semiconductor region;
a third semiconductor region of a second conductivity type provided on the second semiconductor region;
a plurality of fourth semiconductor regions of a first conductivity type selectively provided on an upper layer portion of the third semiconductor region;
a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region;
a gate insulating film provided on an inner wall of each of the plurality of trenches;
and a gate electrode filled inside each of the gate insulating films,
one side surface of each of the plurality of fourth semiconductor regions is provided so as to be in contact with a side surface of each of the plurality of trenches,
an arrangement interval of the plurality of trenches in the first active region is formed to be wider than the arrangement interval of the plurality of trenches in the second active region.
Yamaguchi discloses (as shown in Fig. 6, 12) wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type ([0086] p+ collector region 2) provided on the second main electrode ([0085] collector electrode 12); (See Fig. 12)
a second semiconductor region ([0086] n- epitaxial region 4 … n+ epitaxial region 3) of a first conductivity type provided on the first semiconductor region (2); ([0086] n- epitaxial region 4 is formed on p+ collector region 2 with n+ epitaxial region 3 therebetween)
a third semiconductor region ([0087] p-type base region 5) of a second conductivity type provided on the second semiconductor region (3,4); (See Fig. 12)
a plurality of fourth semiconductor regions of a first conductivity type ([0085] an n+ emitter region 6) selectively provided on an upper layer portion of the third semiconductor region (5); (See Fig. 12, showing 2 emitter regions 6 on each base region 5)
a plurality of trenches ([0138] trench 1a) penetrating the third semiconductor region (5) and reaching the second semiconductor region (3,4); (See Fig. 12, showing the trench 1a passes through the base region 5 into the n- epitaxial region 4)
a gate insulating film ([0138] gate insulating film 8) provided on an inner wall of each of the plurality of trenches (1a); and a gate electrode ([0138] gate electrode layer 9) filled inside each of the gate insulating films (8), ([0138] that gate electrode layer 9 fills a trench 1a formed at the main surface of semiconductor substrate 1 with gate insulating film 8 interposed therebetween)
one side surface of each of the plurality of fourth semiconductor regions (6) is provided so as to be in contact with a side surface of each of the plurality of trenches (1a), (See Fig. 12)
Okuda teaches that the semiconductor device can be a MOSFET or IGBT. ([0046] The semiconductor device 11 according to this embodiment is constituted by a power MOSFET or IGBT.) However, Okuda only discloses the structure of a vertical MOSFET. Yamaguchi discloses the structure of a vertical IGBT. Therefore,, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the structure of the IGBT as disclosed in Yamaguchi to make the IGBT version of the device in Okuda.
However, Okuda in view of Yamaguchi fails to disclose an arrangement interval of the plurality of trenches in the first active region is formed to be wider than the arrangement interval of the plurality of trenches in the second active region.
Kanamaru discloses (as shown in Figs. 1) an arrangement interval of the plurality of trenches in the first active region is formed to be wider than the arrangement interval of the plurality of trenches in the second active region. ([0015] The interval between the unit cells 4 is large in the central part 11 of the chip and small in the peripheral part 12 of the chip)
Kanamaru teaches that the it is preferable that the base layer through which a current flows is densely arranged in the peripheral portion of the chip having a small amount of heat generation, and sparsely arranged in the central portion of the chip having a large amount of heat generation. ([0012]) Kanamaru further teaches that this arrangement reduces the temperature imbalance between the central and peripheral regions. ([0013] According to the present invention, the heat radiation at the central portion of the chip, which generates a large amount of heat, is improved, so that the temperature imbalance in the chip surface is reduced, and a uniform temperature distribution is obtained.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the arrangement interval of the plurality of trenches in the first active region is formed be wider than the arrangement interval of the plurality of trenches in the second active region in order to reduce the temperature difference between the parts of the chip.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuda as applied to claim 1 above, and further in view of Yamaguchi (US 2012/0025263 A1) and Hatori (US 2011/0316071 A1).
Regarding Claim 6, Okuda further discloses (as shown in Fig. 19a) a first semiconductor region of a first conductivity type ([0130] With reference to FIGS. 19A and 19B, the previously described substrate 2 includes an n+ type semiconductor substrate 20 and an n- type epitaxial layer 55 formed on the semiconductor substrate 20.) provided on the second main electrode; ([0131] the drain metal 57 is formed on the rear surface side of the substrate 2)
a second semiconductor region of a second conductivity type ([0133] a p type body region 28) provided on the first semiconductor region (2); (See Fig. 19A)
a plurality of third semiconductor regions of a first conductivity type selectively ([0133] An n+ type source region 27) provided on an upper layer portion of the second semiconductor region (28);
a plurality of trenches ([0131] trench 24) penetrating the second semiconductor region (28) and reaching the first semiconductor region (2); (See fig. 19A, showing the gate trenches 24 pass through the body region 28 into the substrate 2)
a gate insulating film ([0131] gate insulating film 25) provided on an inner wall of each of the plurality of trenches (24); and a gate electrode ([0131] gate electrode 26) filled inside each of the gate insulating films (25), ([0131] The previously described trench gate structures 54 are made in the surface part of the epitaxial layer 55, and includes the trench 24 dug through the epitaxial layer 55 and the gate electrode 26 embedded in the trench 24 with the gate insulating film 25 sandwiched therebetween.)
one side surface of each of the plurality of third semiconductor regions (27) is provided so as to be in contact with a side surface of each of the plurality of trenches (24) (See Fig. 19A)
However, Okuda fails to disclose wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type provided on the second main electrode;
a second semiconductor region of a first conductivity type provided on the first semiconductor region;
a third semiconductor region of a second conductivity type provided on the second semiconductor region;
a plurality of fourth semiconductor regions of a first conductivity type selectively provided on an upper layer portion of the third semiconductor region;
a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region;
a gate insulating film provided on an inner wall of each of the plurality of trenches;
and a gate electrode filled inside each of the gate insulating films,
one side surface of each of the plurality of fourth semiconductor regions is provided so as to be in contact with a side surface of each of the plurality of trenches,
an impurity concentration of the first semiconductor region in the first active region is set to be lower than an impurity concentration of the first semiconductor region in the second active region.
Yamaguchi discloses (as shown in Fig. 6, 12) wherein the semiconductor substrate includes:
a first semiconductor region of a second conductivity type ([0086] p+ collector region 2) provided on the second main electrode ([0085] collector electrode 12); (See Fig. 12)
a second semiconductor region ([0086] n- epitaxial region 4 … n+ epitaxial region 3) of a first conductivity type provided on the first semiconductor region (2); ([0086] n- epitaxial region 4 is formed on p+ collector region 2 with n+ epitaxial region 3 therebetween)
a third semiconductor region ([0087] p-type base region 5) of a second conductivity type provided on the second semiconductor region (3,4); (See Fig. 12)
a plurality of fourth semiconductor regions of a first conductivity type ([0085] an n+ emitter region 6) selectively provided on an upper layer portion of the third semiconductor region (5); (See Fig. 12, showing 2 emitter regions 6 on each base region 5)
a plurality of trenches ([0138] trench 1a) penetrating the third semiconductor region (5) and reaching the second semiconductor region (3,4); (See Fig. 12, showing the trench 1a passes through the base region 5 into the n- epitaxial region 4)
a gate insulating film ([0138] gate insulating film 8) provided on an inner wall of each of the plurality of trenches (1a); and a gate electrode ([0138] gate electrode layer 9) filled inside each of the gate insulating films (8), ([0138] that gate electrode layer 9 fills a trench 1a formed at the main surface of semiconductor substrate 1 with gate insulating film 8 interposed therebetween)
one side surface of each of the plurality of fourth semiconductor regions (6) is provided so as to be in contact with a side surface of each of the plurality of trenches (1a), (See Fig. 12)
Okuda teaches that the semiconductor device can be a MOSFET or IGBT. ([0046] The semiconductor device 11 according to this embodiment is constituted by a power MOSFET or IGBT.) However, Okuda only discloses the structure of a vertical MOSFET. Yamaguchi discloses the structure of a vertical IGBT. Therefore,, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use the structure of the IGBT as disclosed in Yamaguchi to make the IGBT version of the device in Okuda.
However, Okuda in view of Yamaguchi fails to disclose an impurity concentration of the first semiconductor region in the first active region is set to be lower than an impurity concentration of the first semiconductor region in the second active region.
Hatori discloses (as shown in Fig. 3-4) an impurity concentration of the first semiconductor region in the first active region ([0081] As shown in FIG. 3 and FIG. 4, the collector layer 200A is roughly divided into a part 201 located in the central portion 41) is set to be lower than an impurity concentration of the first semiconductor region in the second active region [0081] As shown in FIG. 3 and FIG. 4, the collector layer 200A is roughly divided into a… part 202 located in the peripheral portion 42.) ([0081] In particular, the impurity concentration of the part 201 corresponding to the central portion 41 is set to be lower than the impurity concentration of the part 202 corresponding to the peripheral portion 42 (see FIG. 4). That is, the impurity concentration of the collector layer 200A is lower in the central portion 41 than the peripheral portion 42)
Hatori teaches that lowering the impurity concentration of the collector layer in the central region of the device lowers the efficiency of the hole injections and thereby increases the resistance to current flow. ([0083] The collector layer 200A having the above-mentioned impurity concentration distribution makes the injection efficiency of the holes injected to the drift layer 110 from the collector layer 200A lower in the central portion 41 than the peripheral portion 42. As a result, the resistance to the current flowing in the substrate thickness direction 103 becomes higher in the central portion 41 than the peripheral portion 42.) Hatori further teaches that this reduces the current and thereby the temperature in the center region, thereby improving the reliability of the power cycle life. ([0084] The resistance control structure 300A reduces the current (more specifically, current density thereof) flowing through the substrate 100A in the thickness direction 103 in the central portion 41 than the peripheral portion 42. Therefore, heat generation due to the current is reduced in the central portion 41, and accordingly a temperature rise in the central portion 41 is reduced. The temperature of the central portion 41 greatly affects the temperature of the entire substrate, whereby it is possible to reduce a temperature rise of the entire substrate. As a result, it is possible to improve the reliability of a power cycle life or the like.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have impurity concentration of the first semiconductor region (central region) in the first active region is set to be lower than an impurity concentration of the first semiconductor region in the second active region (peripheral region) in order to improve the reliability of the power life cycle.
Conclusion
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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