Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "the detector" in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 10749519 B2 and Wada hereinafter.) in view of Matsubara et al. (US 11271560 and Matsubara hereinafter.).
Regarding claim 9, Wada discloses [fig. 4 and 5] gate drive circuitry [110] configured to make a first main switching element [10] a target to be driven. Wada discloses further the gate drive circuitry comprising: a controller [110 and 150] configured to: make output to a gate terminal of the first main switching element in a high-impedance state for a prescribed period [driving signal is low during 210 of fig. 4 making 10 high impedance] when a drain-source voltage of the first main switching element fluctuates during a turn-on action period [Vds dropping from high to low during 210] that is a period from a state change of the first main switching element to completion of turning on of the first main switching element [Ssw high during 210], wherein the state change is a change from a state in which the first main switching element is kept turned off to a state in which the first main switching element is in a turn-on state [Sdr low during 210], the drain-source voltage of the first main switching element being completely lowered when the turning on of the first main switching element is completed [Vds going from high to low during 210]: and return the output to the gate terminal of the first main switching element to a turn-on action state after the prescribed period ends [driving signal high after 210], the turn-on action state being a state observed before a start of the prescribed period [driving signal high before 210], and continuing a turn-on action until the turning on of the first main switching element is completed [driving signal high after 210], wherein the prescribed period continues until a gate current of the first main switching element temporarily becomes zero, or until the drain-source voltage of the first main switching element and a drain-source voltage of the second main switching element temporarily stop changing [drain voltage reaches zero after 210 completes]. Wada does not explicitly disclose wherein the first main switching element and a second main switching element are connected in series.
However, Matsubara discloses [fig. 1] the first main switching element [4] and a second main switching element [3] are connected in series [as shown]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Wada to include the first main switching element and a second main switching element are connected in series as taught by Matsubara to improve prevention of turn-off loss in a transistor switching circuit.
Regarding claim 10, Wada in view of Matsubara discloses further comprising a detector configured to detect a timing serving as a trigger to start the prescribed period [Wada, 120 and 130 creating Ta], wherein the detector is configured to: detect a timing as the timing serving as the trigger to start the prescribed period [Wada, col 8 lines 8-18]; and output, to the controller, a signal indicating that the timing serving as the trigger to start the prescribed period has been detected [Wada, col 8 lines 8-18], the detected timing being a timing at which a first current value reaches a peak and starts to decrease so as to converge [Matsubara, Id1 reaching a max level and then decreasing as shown in fig. 3], the peak exceeding a second current value [Matsubara, Id2], the first current value being a current value of a current flowing through the first main switching element [Matsubara, current through 1], the second current value being a current value of a current flowing through the second main switching element [Matsubara, current through 2] when the first main switching element is in the state in which the first main switching element is kept turned off, and the controller is configured to make the output to the gate terminal of the first main switching element in the high-impedance state for the prescribed period after a prescribed delay time elapses after acquisition of the signal [Both switches turned off].
Regarding claim 11, further comprising a detector configured to detect a timing serving as a trigger to start the prescribed period [Wada, 120 and 130 creating Ta], wherein the detector is configured to: detect a timing as the timing serving as the trigger to start the prescribed period [Wada, col 8 lines 8-18]; and output, to the controller, a signal indicating that the timing serving as the trigger to start the prescribed period has been detected [Wada, Wada, col 8 lines 8-18], the detected timing being a timing at which the drain-source voltage starts to decrease [Wada, vds dropping during 210 shown in fig. 4], the drain-source voltage being applied to the first main switching element, and the controller is configured to make the output to the gate terminal of the first main switching element in the high-impedance state for the prescribed period after a prescribed delay time elapses [Wada, via 130] after acquisition of the signal [Wada, driving signal low during 210].
Regarding claim 12, Wada in view of Matsubara discloses further comprising a detector configured to detect a timing serving as a trigger to start the prescribed period [Wada, 120 and 130 creating Ta], wherein the detector is configured to: detect a timing as the timing serving as the trigger to start the prescribed period [Wada, col 8 lines 8-18]; and output, to the controller, a signal indicating that the timing serving as the trigger to start the prescribed period has been detected [Wada, col 8 lines 8-18], the detected timing being a timing at which an amount of change in gate voltage has decreased to enter a mirror region [Wada, gate voltage constant for part of 200], the gate voltage being applied to the first main switching element, the gate voltage being a mirror voltage in the mirror region [constant gate voltage], and as a result of acquiring the signal, the controller is configured to: presume that the drain-source voltage of the first main switching element has started to decrease [Wada, Vg decreasing during 200]; and make the output to the gate terminal of the first main switching element in the high-impedance state for the prescribed period after a prescribed delay time elapses after acquisition of the signal [Wada, 10 eventually turning off].
Regarding claim 13, Wada in view of Matsubara discloses further wherein when detecting the timing serving as the trigger to start the prescribed period, the detector is configured to output a pulse signal as the signal to the controller for a prescribed period [Wada, col 8 lines 8-18], the pulse signal being in a state different from a state observed before detection of the timing [no signal before Ta begins].
Regarding claim 14, Wada in view of Matsubara discloses further wherein when detecting the timing serving as the trigger to start the prescribed period, the detector is configured to output a pulse signal as the signal to the controller for a prescribed period [Wada, col 8 lines 8-18], the pulse signal being in a state different from a state observed before detection of the timing [no signal before Ta begins].
Regarding claim 15, Wada in view of Matsubara discloses further wherein when detecting the timing serving as the trigger to start the prescribed period, the detector is configured to output a pulse signal as the signal to the controller for a prescribed period [Wada, col 8 lines 8-18], the pulse signal being in a state different from a state observed before detection of the timing [no signal before Ta begins].
Regarding claim 16, Wada in view of Matsubara discloses further comprising: a first switching element [Wada, 151] with one end connected to a first direct-current power supply [Wada, Vh], the first switching element being capable of outputting a voltage from another end [Wada, 151 coupled to 15] to the gate terminal of the first main switching element [Wada, 10]; and a second switching element [Wada, 152] with one end connected to a second direct-current power supply [Wada, Vss], the second switching element being capable of outputting a voltage from another end to the gate terminal of the first main switching element [Wada, 152 coupled to 15], wherein by individually controlling on/off of the first switching element and the second switching element, the controller is configured to: control the voltages to be output to the gate terminal of the first main switching element [Wada, 150 driving 10]; or make the output to the gate terminal of the first main switching element in the high-impedance state [Wada, 10 turned off].
Regarding claim 17, Wada in view of Matsubara discloses further wherein the controller includes: a control circuitry configured to output control signals for controlling the on/off of the first switching element and the second switching element [Wada, 110 acting as control circuitry to control 150]; and a buffer configured to turn on and off the first switching element and the second switching element by amplifying the control signals [Wada, 145 acting as a summing buffer], and the buffer has a function of controlling operation of the first switching element and the second switching element and making the output to the gate terminal of the first main switching element in the high-impedance state [Wada, 151 bring turned off], based on a signal acquired from the detector configured to detect a timing serving as a trigger to start the prescribed period, the signal indicating that the timing serving as the trigger to start the prescribed period has been detected [Wada, 120 and 130 acting as detectors and triggering timing events].
Regarding claim 18, Wada in view of Matsubara discloses further comprising: a first constant-current circuitry [Wada, 151] with one end connected to a first direct-current power supply [Wada, Vh], the first constant-current circuitry being capable of outputting a current from another end to the gate terminal of the first main switching element [150 driving 10]; and a second constant-current circuitry [Wada, 152] with one end connected to a second direct-current power supply [Wada, Vss], the second constant-current circuitry being capable of outputting a current from another end to the gate terminal of the first main switching element [150 driving 10], wherein by individually controlling the first constant-current circuitry and the second constant- current circuitry, the controller is configured to: control the currents to be output to the gate terminal of the first main switching element [150 driving 10]; or make the output to the gate terminal of the first main switching element in the high-impedance state [10 turned off].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Morishita (JP 2018157617) is cited to teach a gate potential controller for use in switching ON or OFF of switching elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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