Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
This is in response to communications filed on 10/14/24.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “the data line bypass module” in line 5. It is not clear whether it is same or different from the “bypass module” recited in line 4. It is necessary to establish a relationship. For the rest of the action, it is taken that the same relationship is intended.
Claims 10-13 depend on claim 9 and incorporate the ambiguities.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 20 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 20 mentions “each transistor is replaced with a reed switch.” However, claim 20 depends claim 14 and claim 17 to inherit the transistors. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 9, 14-15, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabitaille et al (US Patent Application Publication 20160313776), and further in view of Fu et al (US Patent Application Publication 20190068479).
For claim 1, Rabitaille et al teach the following limitations: A port assembly for a daisy chain topology (Fig 2; 60 in Fig 7- Ethernet management device; Fig 8 and Fig 11) comprising: a converter configured to receive an input from a device (69 in Fig 7 and Fig 8; PD is a converter); a first t(Fig 3 – Fig 5, contact 50, 51 is part of first switching mechanism) configured to receive an input from the converter (relay control line is shown in Fig 3 – Fig 5; the relay control line 41 is shown in Fig 3; the relay control line receives the input from converter and propagates the input to relay; [0037] – Fig 3 shows 36, which is the converter and provides power to 37 and 38, 37 provides signal to control line 41; [0048][0074][0091][0092]) and a plurality of data lines (Fig 2 – Fig 5; Ethernet port carries data signal; Fig 9 and Fig 10; 34 and 35 are connected to RJ45 port) and a second (39 and 38, 40 in Fig 3, contact 52 in Fig 5) configured to accept a plurality of data lines (Ethernet PHY 39 takes the data lines shown in Fig 3; [0037] – in normal mode same signal will pass from RJ45 connector to 39 and 40 using contact 52) and an input from the first (contact 52 receives the data signal from contact 50; Fig 5; [0037]; thus rest of the circuit 25/38 receives the input from first switching mechanism including contact 50; the first switching mechanism including contact 51 is open – which is considered an input to second switching mechanism 50-52, 39, 38 because no signal can pass through 51 to allow all signal to input 52); and wherein: the converter indicates a power status of the device to the first (status line 41 is shown in Fig 3, Fig 11; power failure/power loss in [0033]-[0034]; [0038]; Fig 11; [0075]), the power status indicates whether the device has power or no power (Fig 11; [0075]; presence or absence power on lines 98 and 100); and if the device has power (Fig 6; step 104), then signals on the data lines are forwarded to the second ([0037] no fault mode, signal will pass through PHY to rest of the circuit; [0048][0053]).
Rabitaille et al do not explicitly mention that the first switching mechanism (including contact 50 to 51) and second switching mechanism (contact 52 connected with 50) include any transistor. Instead, [0004] and [0216] mentions that the switching mechanism can be implemented with double-pole double-throw relays. However, the double-pole double-throw can be implemented with MOSFET (Fu et al; Fig 3; [0096]).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide transistors in the first and second switching mechanisms, since FETs are cheaper, available and fast technology. Implementing switches with transistors offer faster switching speeds, higher reliability and smaller size. It is understood that Fig 4 Fig 5 switches can have transistors in path 50, 51 and 52 to implement the transistor-based switches.
For claim 2, Rabitaille et al teach the following limitations: wherein if the device has no power, then the signals on the data lines bypass the second transistor or reed switching mechanism and go to the device (Fig 4- Fig 6; no power causes relay in the bypass mode) .
For claim 3, Rabitaille et al teach the following limitations: wherein: if an input to the converter is zero then the data on the lines are bypassed by the second transistor or reed switching mechanism (absence of power; total power failure; step 100 in Fig 6; bypass mode is active); and if an input to the converter has a magnitude greater than zero, then the signals on the data lines are forwarded to the second transistor or reed switching mechanism which in turn are forwarded to the device ([0037] step 104 in Fig 6 [0075]; for voltage. Presence, signals forwarded to rest of the circuit as shown in Fig 2).
For claim 4, Fu et al teach wherein the first transistor or reed switching mechanism is configured with FET transistors ([0096]).
For claim 5, Fu et al teach wherein the first transistor or reed switching mechanism is configured with MOSFETs ([0096]).
For claim 9, Rabitaille et al teach the following limitations: A system (Fig 1 – Fig 11) that achieves with ([0033]-[0034] [0037] [0048][0074][0075]; bypass mode connects the switches like Fig 4 and Fig 5 to bypass the rest of the circuit shown in Fig 2-Fig 3; no bypass or normal mode connects the contact 52 so the signal passes to 38, 39 of Fig 3) in an event of loss of power by a device (Fig 11; [0075]; presence or absence power on lines 98 and 100) , comprising: a device power detection module (36 and 37 of Fig 3; [0033]-[0034] [0037][0048] [0075]; presence or absence of power is detected; [0041][0047] – total/partial power failure is detected); a bypass module connected to the device power detection module (23 in Fig 2; 34 and 35 in Fig 3; Fig 4- Fig 5); and an interface module (38, 39 and 40 in Fig 3) connected to the data line bypass module (Fig 3); and wherein: the device power detection module has an input for connection to a device voltage terminal ([0038] Fig 7; [0060][0075] PD has the voltage connection for the device; thus CPU 37 receives power from via 36; 36 receives power from RJ45 Fig 3); the bypass module has an output that indicates the next action relative to data lines in the event of power-on status or power-off status ([0037] Fig 3 Fig 6; power off causes by pass mode and power on causes normal mode; the bypass causes 50 to connect with 51 as shown in Fig 4 and Fig 5; the no bypass or normal mode causes 50 to connect with 52 to pass signal through 38 and 39); if the power-on status is indicated at the device power detection module (CPU senses the status for status line 41 [0037]), then the data lines can pass signals through the bypass detection module and the interface module ([0037] [0053] – normal mode, signal pass from RJ45 connector to the Ethernet PHY 39 and 40 via the relays using contact 52); and if the power-off status is indicated at the device power detection module ([0037][0033][0034][ and [0048]), then the data lines can bypass the interface module ([0037]; fault mode relays connect like Fig 4 and Fig 5 and the data lines do not pass to 38, 39 and 40)
Rabitaille et al do not explicitly mention that the first switching mechanism (including contact 50 to 51) and second switching mechanism (contact 52 connected with 50) include any FET technology. Instead, [0004] and [0216] mentions that the switching mechanism can be implemented with double-pole double-throw relays. However, the double-pole double-throw can be implemented with MOSFET (Fu et al; Fig 3; [0096]).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide FET transistors in the first and second switching mechanisms, since FETs are cheaper, available and fast technology. Implementing switches with transistors offer faster switching speeds, higher reliability and smaller size. It is understood that Fig 4 Fig 5 switches can have transistors in path 50, 51 and 52 to implement the transistor-based switches.
For claim 14, Rabitaille et al teach the following limitations: A port for signal routing topology (Fig 2; 60 in Fig 7- Ethernet management device) comprising: a first (Fig 4 and Fig 5 shows the switch circuit to provide first switch circuit via connection 50 to 51; the circuit includes relays and converter 36 in Fig 3) configured to disconnect and connect (the connection is through 50-51-51-50 in Fig 4 and Fig 5, which disconnect the other path) to bypass a plurality of data lines (bypass is shown in Fig 2, Fig 3 and Fig 6 106; bypass described in [0037]) in the event of a power off of a device ([0033][0034][0037][0040][0041][0047] bypass is triggered by total/partial power failure) and yet keep communication ([0033][0037] – fault mode relays connect together and the Ethernet signal pass from one RJ45 connector to the other via contact 51); and wherein: the first comprises a converter (69 in Fig 7 and Fig 8; PD is a converter) that provides a voltage indicative of a power off or power on status of the device ([0037] – Fig 3 shows 36, which is the converter and provides power to 37 and 38, [0075] – presence or absence of power); and the voltage ensures a connection or disconnection of the plurality of data lines ([0037] – plurality of data is connected to rest of the circuit during normal mode when voltage present; Fig 4 – Fig 6).
Rabitaille et al do not explicitly mention that the first switching mechanism (including contact 50 to 51) and second switching mechanism (contact 52 connected with 50) include any FET technology. Instead, [0004] and [0216] mentions that the switching mechanism can be implemented with double-pole double-throw relays. However, the double-pole double-throw can be implemented with MOSFET (Fu et al; Fig 3; [0096]).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide transistors such as FETs in the first switching mechanisms, since FETs are cheaper, available and fast technology. Implementing switches with transistors offer faster switching speeds, higher reliability and smaller size. It is understood that Fig 4 Fig 5 switches can have transistors in path 50, 51 and 52 to implement the transistor-based switches.
For claim 15, Fu et al teaches wherein the connection or disconnection of the plurality of data lines is performed by one or more FET switches ([0096]).
For claim 17, Rabitaille et al teach a second switch circuit connected to each of the plurality of data lines (Fig 4 and Fig 5; (contact 52 connected with 50) and wherein: a voltage signal to each switch indicates the power on status of the device (relay control signal shown in Fig 3 – Fig 6 and [0037]); and each data line of the plurality of data lines is connected to each switch for communication with the device (presence of voltage triggers no bypass mode; the contact 52 is connected with 50 to pass data signals in the rest of the circuit [0037]). Rabitaille et al do not explicitly mention second switching mechanism (contact 52 connected with 50) include any transistor. Instead, [0004] and [0216] mentions that the switching mechanism can be implemented with double-pole double-throw relays. However, the double-pole double-throw can be implemented with MOSFET (Fu et al; Fig 3; [0096]) as explained above. The circuitries of Fig 4 and Fig 5 of Rabitalle can be implemented with FET.
For claim 18, Rabitaille et al teach wherein the first switch circuit further comprises: a switch connected in series with each data line of the plurality of data lines (Fig 4 and Fig 5; [0037] one pair per wire); and wherein each switch can open or close a connection between each data line and each switch for communication with the device (Fig 4; Fig 5 [0037]). . Rabitaille et al’s relays 34 and 35 can be replaced with transistors as explained above.
For claim 19, Fu et al teach wherein the first transistor or reed switching mechanism is configured with FET transistors ([0096]).
Claim(s) 6-8, 16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabitaille et al (US Patent Application Publication 20160313776), and further in view of Fu et al (US Patent Application Publication 20190068479), further in view of Harp (US Patent Application Publication 20210086810).
For claim 6, Rabitaille in view of Fu does not mention the first transistor or reed switching mechanism is configured with reed switches. Harp teaches that the double pole double throw switch can be implemented with reed switches ([0029] Fig 8). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use reel switches as the DPDT switch in Rabitaille in view of Fu, as reed switch is power saving, offer high reliability and long operational life.
For claim 7, Rabitaille in view of Fu does not mention the second transistor or reed switching mechanism is configured with reed switches. Harp teaches that the double pole double throw switch can be implemented with reed switches ([0029] Fig 8). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use reel switches as the DPDT switch in Rabitaille in view of Fu, as reed switch is power saving, offer high reliability and long operational life.
For claim 8, Harp teaches wherein the reed switches are controlled by a magnet ([0029]).
For claim 16, Rabitaille in view of Fu does not mention reed switches. Harp teaches that the double pole double throw switch can be implemented with reed switches ([0029] Fig 8), which also includes opening and closing. It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use reel switches as the DPDT switch for connection and disconnection of data switches in Rabitaille in view of Fu, as reed switch is power saving, offer high reliability and long operational life.
For claim 20, Rabitaille in view of Fu does not mention reed switches. Harp teaches that the double pole double throw switch can be implemented with reed switches ([0029] Fig 8), which also includes opening and closing of the reed switch by using magnet. It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use reel switches as the DPDT switch for connection and disconnection of data switches in Rabitaille in view of Fu, as reed switch is power saving, offer high reliability and long operational life.
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabitaille et al (US Patent Application Publication 20160313776), and further in view of Fu et al (US Patent Application Publication 20190068479), further in view of Webb et al (US Patent Application Publication 2007/0283173).
For claim 10, Rabitaille in view of Fu mentions power on status can provide a voltage to a PD/PSE (Fig 11; Rabitallie), but does not mention capacitor. Webb teaches a system where PD includes a capacitor 270 to store voltage of transformer as shown in Fig 2. Capacitor is connected as parallel to the transformer, the capacitor is able to store energy at a constant value ([0028] – capacitor provide a relatively smooth DC voltage). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to combine the teachings of Rabitaille, Fu and Webb so that the transformer of the PD/PSE circuit can have a capacitor to filter the ripples and provides relatively smooth voltage. Such smooth voltage optimizes the operation of the circuitries.
Allowable Subject Matter
Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and to overcome 35 USC 112 (b) as set forth in the action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAHMIDA RAHMAN whose telephone number is (571)272-8159. The examiner can normally be reached Monday - Friday 10 AM - 7 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
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