DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kawamura (US 2016/0126610 A1) in view of Herbsommer et al. (US 9,405,064 B2), hereinafter Herb.
Regarding claim 1, Kawamura discloses, in figure 1, a mode transition structure, comprising:
a first dielectric substrate that includes a microstrip line including a line conductor and a first ground conductor facing the line conductor and that has a first thickness (Para [0055], “microstrip line 10 is formed such that a strip-shaped main conductor 12 is patterned on one surface of a dielectric substrate 11 from one end to the other end, the other surface is covered with a ground conductor 13”); and
a second dielectric substrate that has a second thickness larger than the first thickness (second dielectric substrate formed by waveguide 20 comprised of metal walls 22a to 22d has a second thickness larger than the first thickness of the first dielectric substrate), but fails to disclose a second dielectric substrate that includes a post-wall waveguide including a first conductor layer connected to the line conductor on a same plane and a second conductor layer facing the first conductor layer; and
a first via that electrically connects the first ground conductor and the second conductor layer to each other.
However, Herb discloses, in figure 10 & 12, a second dielectric substrate that includes a post-wall waveguide (Col. 13, Lines 24-26, “metal waveguide 322 in which the core 310-C of the dielectric waveguide 204-C extends…part of PCB 202-C”) including a first conductor layer connected to the line conductor on a same plane and a second conductor layer facing the first conductor layer (first conductor layer 404 is connected to microstrip line conductor 320-1 on a same plane and includes a second conductor layer 402 facing the first conductor layer 404); and
a first via that electrically connects the first ground conductor and the second conductor layer to each other (Col. 13, Lines 40-43, “vias 408 are shown in this example as extended between plate 402 and ground plane 308-C so that plates 402 and 404 and ground plane 308-C are electrically coupled together”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the structure of Herb in the mode transition structure of Kawamura, to achieve the benefit of achieving a desired coupling while incorporating improved impedance matching between the microstrip and waveguide structures (Herb, Col. 13, Lines 25-40).
Allowable Subject Matter
Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
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/TYLER J PERENY/ Examiner, Art Unit 2842