DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 12/10/25 have been fully considered but they are not persuasive. Applicant argues the cited prior art fails to teach 1) "determine, using the MV precision, whether to omit decoding least significant bits of offset bits of the integer portion and to set the least significant bits of offset nits of the integer portion to a predefined value", 2) "wherein to decode, using the MV precision and the MV class, the at least the subset of bits representing the integer portion of the MVD comprises to infer that at least one least significant bit of bits representing the integer portion of the MVD is zero based on the MV precision" and 3) "decode, from a compressed bitstream and based on the MV precision, a subset of bits of fractional portion of the MVD." In the cited prior art Deng the ”class” refers to a range and multiple sets of ranges may be defined. [¶ 0171] Within the decoding memory K bits are assigned to represent the integer portion and L bits are assigned to represent the fractional portion, wherein K and L are positive integers, cf. e.g. the case of VVC with K = 13 and L = 4, recalled in paragraph. [¶ 0078-0101; ¶ 0173] A parameter L representing precision integer in both positive and negative values; for a precision L ≤ 0 and according to the class, defined by the range, in the case of a decoded or signaled MVD component [¶ 0160], K - |L| bits are decoded for representing the integer part of MVD at decoding, whereas the least significant |L| bits of the K bits used for representing the integer part, are set to 0 in the decoding memory. Deng discloses "the value of MVD component is constrained and/or clipped to be in the range", as "constraining and/or clipping" means in context to set the least significant bits to 0 in the decoding memory. [¶ 0160] Motion vector difference (MVD) is obtained in the encoding/decoding process. The cited prior art fairly suggest and teaches the limitations as presented. Therefore the rejection is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-17 and 24-26 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Deng et al. US 2021/0385462.
As to claim 1, Deng teaches an apparatus for decoding a current block, comprising: a processor [fig. 2; ¶ 0121] configured to: decode, from a compressed bitstream, a motion vector (MV) class of a motion vector difference (MVD) for the current block, wherein the MV class is indicative of a set of MVDs, each MVD of the set of MVDs corresponds to respective integer portions, and wherein the MVD comprises an integer portion and a fractional portion; [figs. 1-2; ¶ 0004; ¶ 0018; ¶ 0043-0045; ¶ 0078-0101; ¶ 0170-0173] obtaining an MV precision of the MVD; [0078-0101] determine, using the MV precision, whether to omit decoding least significant bits of offset bits of the integer portion and to set the least significant bits of offset bits of the integer portion to a predefined value; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-0165] decode at least some of the offset bits; [¶ 0070-0101] obtaining obtain the integer portion using the at least some of the offset bits and the least significant bits of the integer portion; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-0165; ¶ 0170-0185] determine, using the MV precision, whether to omit decoding and to set, to the predefined value, least significant bits of fractional bits of the fractional portion; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-165; ¶ 0170-0185] decode the at least some of the fractional bits for the fractional portion; [¶ 0070-0101] obtain the fractional portion using the at least some of the fractional bits and the least significant bits of the fractional portion; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-165; ¶ 0170-0185] obtain the MVD using at least the integer portion and the fractional portion; [¶ 0070-0185] obtain a motion vector for the current block using the MVD; [fig. 1; ¶ 0022; ¶ 0025; ¶ 0078-0101; ¶ 0170-0195] and obtain a prediction block for the current block using the motion vector. [fig. 1; ¶ 0041; ¶ 0170-0195]
As to claim 2, Deng teaches the limitations of claim 1. Deng teaches wherein the least significant bits of the offset bits of the integer portion constitute 2 bits in a case that the MV precision indicates a 4-integer pixel magnitude. [¶ 0030; ¶ 0042-0045; ¶ 0048; ¶ 0078-0101; ¶ 0160-0165; ¶ 0170-0174]
As to claim 3, Deng teaches the limitations of claim 1. Deng teaches wherein the least significant bits of the offset bits of the integer portion constitute 1 bit in a case that the MV precision indicates a 2-integer pixel magnitude. [¶ 0042-0045; ¶ 0048; ¶ 0078-0101; ¶ 0160-0165; ¶ 0170-0174]
As to claim 4, Deng teaches the limitations of claim 1. Deng teaches wherein the least significant bits of the fractional portion constitute the least significant bit in a case that the MV precision indicates a precision that is not finer than a ¼ pixel precision. [¶ 0042-0045; ¶ 0055]
As to claim 5, Deng teaches the limitations of claim 1. Deng teaches wherein the least significant bits of the fractional portion constitute two least significant bits in a case that the MV precision indicates a precision that is not finer than a ½ pixel precision. [¶ 0042-0045; ¶ 0170-0195]
As to claim 6, Deng teaches an apparatus for decoding a current block, comprising: a processor [fig. 2; ¶ 0121] configured to: decode, from a compressed bitstream, a motion vector (MV) class of a motion vector difference (MVD) of the current block, wherein the MV class is indicative of a set of MVDs, and wherein the MVD includes an integer portion; [figs. 1-2; ¶ 0004; ¶ 0018; ¶ 0043-0045; ¶ 0078-0101; ¶ 0170-0173] obtain an MV precision of the MVD; [0078-0101] decode, using the MV precision and the MV class, at least a subset of bits representing the integer portion of the MVD; [figs. 1-2; ¶ 0004; ¶ 0018; ¶ 0043-0045; ¶ 0078-0101; ¶ 0170-0173] obtain the MVD using the bits representing the integer portion of the MVD; [figs. 1-2; ¶ 0004; ¶ 0018; ¶ 0043-0045; ¶ 0078-0101; ¶ 0170-0173] obtain a motion vector for the current block using the MVD; [fig. 1; ¶ 0022; ¶ 0025; ¶ 0078-0101; ¶ 0170-0195] and obtain a prediction block for the current block using the motion vector. [fig. 1; ¶ 0041; ¶ 0170-0195]
As to claim 7, Deng teaches the limitations of claim 6. Deng teaches wherein to decode, using the MV precision and the MV class, the at least the subset of bits representing the integer portion of the MVD comprises to: infer that at least one least significant bit of bits representing the integer portion of the MVD is zero based on the MV precision. [¶ 0030; ¶ 0043-0045; ¶ 0048; ¶ 0068-0101; ¶ 0170-0173]
As to claim 8, Deng teaches the limitations of claim 6. Deng teaches wherein to decode, using the MV precision and the MV class, the at least the subset of bits representing the integer portion of the MVD comprises to: responsive to determining that the MV precision indicates a 4-integer pixel magnitude, infer that two least significant bits of the bits representing the integer portion are zero. [¶ 0030; ¶ 0043-0045; ¶ 0048; ¶ 0068-0101; ¶ 0170-0173]
As to claim 9, Deng teaches the limitations of claim 6. Deng teaches wherein to decode, using the MV precision and the MV class, the at least the subset of bits representing the integer portion of the MVD comprises to: responsive to determining that the MV precision indicates a 2-integer pixel magnitude, infer that one least significant bit of the bits representing the integer portion are zero. [¶ 0030; ¶ 0043-0045; ¶ 0048; ¶ 0068-0101; ¶ 0170-0173]
As to claim 10, Deng teaches the limitations of claim 6. Deng teaches wherein the processor is configured to: decode, using the MV precision, at least a subset of bits representing a fractional portion of the MVD. [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-165; ¶ 0170-0185]
As to claim 11, Deng teaches the limitations of claim 10. Deng teaches wherein to decode, using the MV precision, the at least the subset of bits representing the fractional portion of the MVD comprises to: responsive to determining that the MV precision indicates a precision that is not finer than a ¼ pixel precision, infer that a least significant bit of the bits representing the fractional portion is zero. [¶ 0030; ¶ 0042-0045; ¶ 0048; ¶ 0055; ¶ 0068-0101; ¶ 0170-0173]
As to claim 12, Deng teaches the limitations of claim 10. Deng teaches wherein to decode, using the MV precision, the at least the subset of bits representing the fractional portion of the MVD comprises to: responsive to determining that the MV precision indicates a precision that is not finer than a ½ pixel precision, infer that two least significant bits of the bits representing the fractional portion are zero. [¶ 0030; ¶ 0042-0045; ¶ 0048; ¶ 0068-0101; ¶ 0170-0195]
As to claim 13, Deng teaches the limitations of claim 10. Deng teaches wherein to decode, using the MV precision, the at least the subset of bits representing the fractional portion of the MVD comprises to: responsive to determining that the MV precision indicates an integer pixel precision, infer that the bits representing the fractional portion are zero. [¶ 0030; ¶ 0043-0045; ¶ 0048; ¶ 0068-0101; ¶ 0170-0173]
As to claim 14, Deng teaches the limitations of claim 6. Deng teaches wherein the processor is configured to: obtain candidate MVs for the MV; [fig. 1; ¶ 0022; ¶ 0025; ¶ 0078-0101; ¶ 0170-0195] and set respective precisions of at least some of the candidate MVs to the MV precision. [¶ 0080-0081; ¶ 0155-0158]
As to claim 15, Deng teaches an apparatus comprising: a processor [fig. 2; ¶ 0121] configured to: obtain a motion vector (MV) precision of a motion vector difference (MVD) of a current block; [0078-0101] decode, from a compressed bitstream and based on the MV precision, a subset of bits of a fractional portion of the MVD; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-165; ¶ 0170-0185] set remaining bits of the fractional portion of the MVD to zero; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-165; ¶ 0170-0185] obtaining the MVD using at least the fractional portion; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-165; ¶ 0170-0185] obtaining a motion vector for the current block using the MVD; [fig. 1; ¶ 0022; ¶ 0025; ¶ 0078-0101; ¶ 0170-0195] and obtaining a prediction block for the current block using the motion vector. [fig. 1; ¶ 0041; ¶ 0170-0195]
As to claim 16, Deng teaches the limitations of claim 15. Deng teaches wherein the processor is configured to: decode, from the compressed bitstream, an MV class of the MVD, wherein the MV class is indicative of a set of MVDs, each MVD of the set of MVDs corresponds to respective integer portions; [¶ 0042-0045; ¶ 0070-0101; ¶ 0160-0165; ¶ 0170-0185] and decode, from the compressed bitstream, an integer portion of the MVD. [figs. 1-2; ¶ 0004; ¶ 0018; ¶ 0043-0045; ¶ 0078-0101; ¶ 0170-0173]
As to claim 17, Deng teaches the limitations of claim 15. Deng teaches wherein the processor is configured to: obtain candidate MVs for the MV; [fig. 1; ¶ 0022; ¶ 0025; ¶ 0078-0101; ¶ 0170-0195] and convert an MV precision of a candidate MV of the candidate MVs to match the MV precision. [¶ 0080-0081; ¶ 0155-0158]
As to claim 24, Deng teaches the limitations of claim 15. Deng teaches wherein to decode, from the compressed bitstream and based on the MV precision, the subset of bits of the fractional portion of the MVD, the processor is configured to: responsive to determining that the MV precision indicates a precision that is not finer than a 1/4 pixel precision, infer that a least significant bit of the bits representing the fractional portion is zero. [¶ 0042-0045; ¶ 0055]
As to claim 25, Deng teaches the limitations of claim 15. Deng teaches wherein to decode, from the compressed bitstream and based on the MV precision, the subset of bits of the fractional portion of the MVD, the processor is configured to: responsive to determining that the MV precision indicates a precision that is not finer than a 1/2 pixel precision, infer that two least significant bits of the bits representing the fractional portion are zero. [¶ 0042-0045; ¶ 0170-0195]
As to claim 26, Deng teaches the limitations of claim 15. Deng teaches wherein to decode, from the compressed bitstream and based on the MV precision, the subset of bits of the fractional portion of the MVD, the processor is configured to: responsive to determining that the MV precision indicates an integer pixel precision, infer that all bits representing the fractional portion are zero. [¶ 0170-0195]
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANNER HOLDER/Primary Examiner, Art Unit 2483