Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu et al. (CN 207264753 U), provided by the applicant on the record along with machine translation.
Regarding claim 1, Zhu discloses a display substrate, comprising:
a base substrate comprising a display region, wherein the display region comprises a plurality of display partitions (see e.g. in Fig. 1, display panel 110 clearly comprising a base substrate comprising a display region including display partitions 112);
a plurality of sub-pixels located in the display region (e.g. pixels structures in the display panel 110; para[0028]); and
a plurality of drive circuits, wherein at least one drive circuit of the plurality of drive circuits corresponds to one display partition (see each drive module 122 corresponds to each display partition 112; para[0028]); and
the at least one drive circuit is configured to provide a gate drive signal to the plurality of sub-pixels within a corresponding display partition to enable display refresh frequencies of the plurality of display partitions to be the same or at least partially different (each “drive module 122 corresponds to a display region 112 to realize the drive of the pixel structure in the display area 112, so as to perform display control of the display region 112”, by controlling refresh frequency of each display area 112 to be “the same or… different”; “the corresponding driving module comprises a scanning drive circuit” that provides scanning signals to pixel structures through a corresponding scanning line; para[0011]; para[0028]).
Regarding claim 2, Zhu discloses all the claim limitations as applied above (see claim 1). In addition, Zhu discloses the plurality of display partitions at least comprises a first partition and a second partition, and the first partition and the second partition are adjacent along a direction (see display partitions 112 in Fig. 1); and
the plurality of drive circuits comprises at least one first drive circuit and at least one second drive circuit (see e.g. a first and a second module 122 in Fig. 1); wherein the at least one first drive circuit is configured to provide a gate drive signal to the plurality of sub-pixels within the first partition, and the at least one second drive circuit is configured to provide a gate drive signal to the plurality of sub-pixels within the second partition (each “drive module 122 corresponds to a display region 112 to realize the drive of the pixel structure in the display area 112, so as to perform display control of the display region 112” and provides scanning signals to pixel structures in each corresponding display region/area/partition 112 through a corresponding scanning line; accordingly, a first drive module 122 provides a scanning signal to pixel structures in first partition 112, and a second drive module 122 provides a scanning signal to pixel structures in second partition 112; para[0011]; para[0028]).
Regarding claim 17, Zhu discloses all the claim limitations as applied above (see claim 1). In addition, Zhu discloses a display apparatus, comprising a display substrate according to claim 1 (para[0007]; para[0026]; “A display device comprises a display panel”, as shown in Fig. 1).
Regarding claim 18, Zhu discloses all the claim limitations as applied above (see claim 1). In addition, Zhu discloses a control method for a display substrate, applied to the display substrate according to claim 1 (para[0037]), wherein the control method comprises: providing, by the at least one drive circuit, the gate drive signal to the plurality of sub-pixels within the display partition corresponding to the at least one drive circuit, to cause the display refresh frequencies of the plurality of display partitions to be the same or at least partially different (each “drive module 122 corresponds to a display region 112 to realize the drive of the pixel structure in the display area 112, so as to perform display control of the display region 112”, by controlling refresh frequency of each display area 112 to be “the same or… different”; “the corresponding driving module comprises a scanning drive circuit” that provides scanning signals to pixel structures through a corresponding scanning line; para[0011]; para[0028]; para[0037]); wherein the at least one drive circuit corresponds to one display partition (see each drive module 122 corresponds to each display partition 112; para[0028]; para[0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), in view of Fu (CN109697966 A), both provided by the applicant on the record along with corresponding machine translations.
Regarding claim 3, Zhu discloses all the claim limitations as applied above (see claim 1). However, Zhu does not appear to expressly disclose a first control circuit connected between the first drive circuit and an second drive circuit adjacent to the first drive circuit, wherein the first control circuit is configured to control display refresh frequencies of the first partition and the second partition to be the same or different.
Fu discloses a first control circuit connected between a first drive circuit and an second drive circuit adjacent to the first drive circuit, wherein the first control circuit is configured to control display refresh frequencies of a first partition and a second partition to be the same or different (see e.g. in Fig. 3, first switching unit 120 and second switch unit 130 connected between register group 110-1 (claimed first drive circuit) and register group 110-2 (claimed second drive circuit), to control refresh frequencies of a first partition connected to 110-1 and of a second partition connected to 110-2 to be the same or different; e.g. “In full display mode, the picture refresh frequency is normal”, “By controlling at least two first switch units 120 to be turned on at the same time, and controlling at least one second switch unit 130 to be turned off at the same time,… all shift register groups [110] can output drive signals step by step, so that the pixel array of the entire display area is scanned and the light-emitting state will be updated” and thus at the same frequency; also e.g. “In the partial area display mode, the picture refresh frequency is relatively high”, “By controlling at least two first switch units 120 to be turned off at the same lime, and controlling at least one second switch unit 130 to be turned on at the same time,… all even-numbered shift register groups [110] can output drive signals step by step, so that the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all even-numbered shift register groups 110 are scanned, and the luminous state will be updated, and the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all odd-numbered shift register groups 110 are not scanned, and the luminous state will not be updated, and the previous luminous state is maintained”, thus updating even and odd shift register groups 110 at different frequencies; para[0017]; para[0043]-para[0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s invention, with the teachings in Fu’s invention, to have a first control circuit connected between the first drive circuit and an second drive circuit adjacent to the first drive circuit, wherein the first control circuit is configured to control display refresh frequencies of the first partition and the second partition to be the same or different, for the advantage of a configuration that reduces display unevenness and ghosting (para[0017]).
Regarding claim 4, Zhu and Fu disclose all the claim limitations as applied above (see claim 3). In addition, Fu discloses the first drive circuit at least comprises a plurality of cascaded first scan control units, the second drive circuit at least comprises a plurality of cascaded second scan control units (see in Fig. 3 each shift register group 110 comprise cascaded shift registers 111; para[0009]); and
the first control circuit is configured to, under control of a first control line and a second control line, enable an output terminal of a last-stage first scan control unit of the first drive circuit and an input terminal of a first-stage second scan control unit of the second drive circuit to be connected, or to enable a second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit to be connected (as shown in Fig. 3, under control of each line connected to each control end Ctr1 of each first switch unit 120 and to control end Ctr2 of second switch unit 130, commonly connected to line 160, an output terminal S2 of a last shift register 111 of e.g. register group 110-1 and an input terminal S1 of a first shift register 111 of register group 110-2 are connected, or a start signal line 152 and the input terminal S1 of the first shift register 111 of register group 110-2 are connected; para[0017]; para[0043]-para[0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the first drive circuit at least comprises a plurality of cascaded first scan control units, the second drive circuit at least comprises a plurality of cascaded second scan control units; and the first control circuit is configured to, under control of a first control line and a second control line, enable an output terminal of a last-stage first scan control unit of the first drive circuit and an input terminal of a first-stage second scan control unit of the second drive circuit to be connected, or to enable a second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit to be connected, as also taught by Fu, for the advantage of reducing a number of control signal lines, further narrow a border of the display panel, and further increase the screen-to-body ratio (para[0045]).
Regarding claim 5, Zhu and Fu disclose all the claim limitations as applied above (see claim 4). In addition, Fu discloses the first control circuit comprises a first control transistor and a second control transistor (see in Fig. 3 first switch units 120 comprise transistors T1, and second switch units 130 comprise transistors T2); a gate electrode of the first control transistor is electrically connected with the first control line (see in Fig. 3 each line connected to each control end Ctr1 of each transistor T1 and commonly connected to line 160), a first electrode of the first control transistor is electrically connected with the output terminal of the last-stage first scan control unit of the first drive circuit (see e.g. a first electrode of transistor T1 connected to the output terminal S2 of the last shift register 111 of e.g. register group 110-1, as shown in Fig. 3), and a second electrode of the first control transistor is electrically connected with the input terminal of the first-stage second scan control unit of the second drive circuit (see e.g. a second electrode of the transistor T1 that is connected to the output terminal S2 of the last shift register 111 of register group 110-1, is connected to the input terminal S1 of the first shift register 111 of register group 110-2, as shown in Fig. 3); and
a gate electrode of the second control transistor is electrically connected with the second control line (see in Fig. 3 the line connected to the control end Ctr2 of the second switch unit 130 and commonly connected to line 160), a first electrode of the second control transistor is electrically connected with the second start signal line (see e.g. a first electrode of transistor T2 connected to the start signal line 152, as shown in Fig. 3), and a second electrode of the second control transistor is electrically connected with the input terminal of the first-stage second scan control unit of the second drive circuit (see e.g. a second electrode of the transistor T2 is connected to the input terminal S1 of the first shift register 111 of register group 110-2, as shown in Fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the first control circuit comprises a first control transistor and a second control transistor; a gate electrode of the first control transistor is electrically connected with the first control line, a first electrode of the first control transistor is electrically connected with the output terminal of the last-stage first scan control unit of the first drive circuit, and a second electrode of the first control transistor is electrically connected with the input terminal of the first-stage second scan control unit of the second drive circuit; and a gate electrode of the second control transistor is electrically connected with the second control line, a first electrode of the second control transistor is electrically connected with the second start signal line, and a second electrode of the second control transistor is electrically connected with the input terminal of the first-stage second scan control unit of the second drive circuit, as also taught by Fu, for the advantage of effectively achieving the reduction of a number of control signal lines, to narrow a border of the display panel, and increase the screen-to-body ratio (para[0045]).
Regarding claim 6, Zhu discloses all the claim limitations as applied above (see claim 2). However, Zhu does not appear to expressly disclose at least one first data line electrically connected with the plurality of sub-pixels within the first partition and at least one second data line electrically connected with the plurality of sub-pixels within the second partition; and extension direction of the at least one first data line and the at least one second data line are the same, and the at least one first data line and the at least one second data line are in a same layer.
Fu discloses at least one first data line electrically connected with a plurality of sub-pixels within a first partition and at least one second data line electrically connected with the plurality of sub-pixels within the second partition (regarding Figs. 3 and 5, see data lines 170 connected e.g. to pixels corresponding to drive signal lines 140 connected to a first partition connected to register group 110-1, and data lines 170 connected e.g. to pixels corresponding to drive signal lines 140 connected to a second partition connected to register group 110-2; para[0044]; para[0053]-para[0054]); and extension direction of the at least one first data line and the at least one second data line are the same (see extension direction of all the data lines 170 in Fig. 5 are the same), and the at least one first data line and the at least one second data line are in a same layer (para[0054]; it is clear that since the “plurality of data lines 170, and the plurality of data lines and the plurality of scanning lines are insulated and cross-linked to define a plurality of pixel units”, data lines 170 are in a same layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s invention, with the teachings in Fu’s invention, to have at least one first data line electrically connected with a plurality of sub-pixels within a first partition and at least one second data line electrically connected with the plurality of sub-pixels within the second partition; and extension direction of the at least one first data line and the at least one second data line are the same, and the at least one first data line and the at least one second data line are in a same layer, for the advantage of transmitting a data voltage to corresponding pixel units so that the pixel units emit light (para[0055]).
Regarding claim 19, Zhu discloses all the claim limitations as applied above (see claim 1). In addition, Zhu discloses the plurality of display partitions at least comprises: a first partition and a second partition, and the first partition and the second partition are adjacent in a direction (see display partitions 112 in Fig. 1).
However, Zhu does not appear to expressly disclose providing, by the at least one drive circuit, the gate drive signal to the plurality of sub-pixels within the display partition corresponding to the at least one drive circuit comprises: when display refresh frequencies of the first partition and the second partition are the same, the first control circuit enables an output terminal of a last-stage first scan control unit of a first drive circuit and an input terminal of a first-stage second scan control unit of a second drive circuit to be connected under control of a first control line and a second control line; and when the display refresh frequencies of the first partition and the second partition are different, the first control circuit enables a second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit to be connected under control of the first control line and the second control line.
Fu discloses providing, by at least one drive circuit, a gate drive signal to a plurality of sub-pixels within a display partition corresponding to at least one drive circuit comprises: when display refresh frequencies of a first partition and a second partition are the same, a first control circuit enables an output terminal of a last-stage first scan control unit of a first drive circuit and an input terminal of a first-stage second scan control unit of a second drive circuit to be connected under control of a first control line and a second control line (regarding Fig. 3, see a first partition connected to register group 110-1 (claimed first drive circuit) and a second partition connected to register group 110-2 (claimed second drive circuit); “In full display mode, the picture refresh frequency is normal”, “By controlling at least two first switch units 120 to be turned on at the same time, and controlling at least one second switch unit 130 to be turned off at the same time,… all shift register groups [110] can output drive signals step by step, so that the pixel array of the entire display area is scanned and the light-emitting state will be updated” and thus at the same frequency; accordingly, under control of each line connected to each control end Ctr1 of each first switch unit 120 and to control end Ctr2 of second switch unit 130, commonly connected to line 160, an output terminal S2 of a last shift register 111 of e.g. register group 110-1 and an input terminal S1 of a first shift register 111 of register group 110-2 are connected; para[0017]; para[0043]-para[0047]); and
when the display refresh frequencies of the first partition and the second partition are different, the first control circuit enables a second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit to be connected under control of the first control line and the second control line (regarding Fig. 3, “In the partial area display mode, the picture refresh frequency is relatively high”, “By controlling at least two first switch units 120 to be turned off at the same lime, and controlling at least one second switch unit 130 to be turned on at the same time,… all even-numbered shift register groups [110] can output drive signals step by step, so that the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all even-numbered shift register groups 110 are scanned, and the luminous state will be updated, and the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all odd-numbered shift register groups 110 are not scanned, and the luminous state will not be updated, and the previous luminous state is maintained”, thus updating even and odd shift register groups 110 at different frequencies; accordingly, under control of each line connected to each control end Ctr1 of each first switch unit 120 and to control end Ctr2 of second switch unit 130, commonly connected to line 160, a start signal line 152 and the input terminal S1 of the first shift register 111 of register group 110-2 are connected; para[0017]; para[0043]-para[0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s invention, with the teachings in Fu’s invention, to have providing, by the at least one drive circuit, the gate drive signal to the plurality of sub-pixels within the display partition corresponding to the at least one drive circuit comprises: when display refresh frequencies of the first partition and the second partition are the same, the first control circuit enables an output terminal of a last-stage first scan control unit of a first drive circuit and an input terminal of a first-stage second scan control unit of a second drive circuit to be connected under control of a first control line and a second control line; and when the display refresh frequencies of the first partition and the second partition are different, the first control circuit enables a second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit to be connected under control of the first control line and the second control line, for the advantage of reducing display unevenness and ghosting while reducing a number of control signal lines, thus narrowing a border of the display panel, and increasing the screen-to-body ratio (para[0017]; para[0045]).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), in view of Fu (CN109697966 A), both provided by the applicant on the record along with corresponding machine translations, as applied to claim 6 above, and further in view of Xu et al. (US 2018/0366495).
Regarding claim 7, Zhu and Fu disclose all the claim limitations as applied above (see claim 6). However, Zhu and Fu do not appear to expressly disclose within the first partition, the at least one first data line is electrically connected with a first data auxiliary line through a first transfer line, an extension direction of the first transfer line is intersected with an extension direction of the first data auxiliary line, and the first data auxiliary line is extended to the second partition.
Xu discloses within a first partition, at least one first data line is electrically connected with a first data auxiliary line through a first transfer line, an extension direction of the first transfer line is intersected with an extension direction of the first data auxiliary line, and the first data auxiliary line is extended to a second partition (regarding Figs. 1-2, within the upper half of the display array substrate in Fig. 1, at least one data line 122 is connected with an auxiliary data line 123 through connection wire 21, an extension direction of the connection wire 21 is intersected with an extension direction of the auxiliary data line 123, and the auxiliary data line 123 is extended to the lower half of the display array substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s and Fu’s combination, with the teachings in Xu’s invention, to have within the first partition, the at least one first data line is electrically connected with a first data auxiliary line through a first transfer line, an extension direction of the first transfer line is intersected with an extension direction of the first data auxiliary line, and the first data auxiliary line is extended to the second partition, for the advantage of a narrow border design and improved display uniformity for display designs in which data lines conventional path is blocked (para[0019]).
Regarding claim 8, Zhu, Fu and Xu disclose all the claim limitations as applied above (see claim 7). In addition, Xu discloses the first transfer line is located on a side of the first data auxiliary line close to a base substrate, and the first data auxiliary line and the first data line are in a same layer (regarding Figs. 2-3, see connection wire 21 is located on a side of the auxiliary data line 123 close to a base substrate, and the auxiliary data line 123 and the data line 122 are in a same layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the first transfer line is located on a side of the first data auxiliary line close to the base substrate, and the first data auxiliary line and the first data line are in a same layer, as also taught by Xu, for the advantage of achieving a display array substrate with narrow border design and improved display uniformity for display designs in which data lines conventional path is blocked (para[0014]; para[0017]; para[0019]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), provided by the applicant on the record along with machine translation, and further in view of Min et al. (US 2022/0208929).
Regarding claim 9, Zhu discloses all the claim limitations as applied above (see claim 2). However, Zhu does not appear to expressly disclose the plurality of display partitions further comprises a third partition adjacent to the first partition in a first direction, wherein the second partition is located on a same side of the first partition and third partition in a second direction; and the first direction is intersected with the second direction; the plurality of drive circuits comprises one first drive circuit, two second drive circuits, and one third drive circuit, wherein the third drive circuit is configured to provide a gate drive signal to the plurality of sub-pixels within the third partition; and the two second drive circuits are located on two opposite sides of the second partition along the first direction, the first drive circuit is adjacent to the first partition in the first direction, the third drive circuit is adjacent to the third partition in the first direction, the first drive circuit is adjacent to one second drive circuit in the second direction, and the third drive circuit is adjacent to another second drive circuit in the second direction.
Min discloses a plurality of display partitions comprising a third partition adjacent to a first partition in a first direction, wherein a second partition is located on a same side of the first partition and third partition in a second direction (referring to Fig. 9, see e.g. pixels PX in the top right corner of the display area DA taken as comprising the claimed third partition adjacent, in a horizontal direction, to the pixels in the top left corner taken as comprising the claimed first partition, wherein the pixels at the lower portion of the display area DA are taken as the claimed second partition located on a same side of the claimed first partition and third partition in a vertical direction); and the first direction is intersected with the second direction (the horizontal and vertical directions intersected with each other, as shown in Fig. 9); the plurality of drive circuits comprises one first drive circuit, two second drive circuits, and one third drive circuit, wherein the third drive circuit is configured to provide a gate drive signal to the plurality of sub-pixels within the third partition (see scan driving circuits SDC in Fig. 9; “The scan driving circuits SDC may be connected to a plurality of scan lines GW” “configured to sequentially transmit electric signals to the pixels PX” in corresponding partitions; para[0120]-para[0121]; para0178]); and the two second drive circuits are located on two opposite sides of the second partition along the first direction (see in Fig. 9 scan driving circuits SDC located on two opposite sides of the lower portion of the display area DA), the first drive circuit is adjacent to the first partition in the first direction (see in Fig. 9 scan driving circuits SDC adjacent to the pixels in the top left corner of display area DA comprising the claimed first partition, in the horizontal direction), the third drive circuit is adjacent to the third partition in the first direction (see in Fig. 9 scan driving circuits SDC adjacent to the pixels PX in the top right corner of display area DA comprising the claimed third partition, in the horizontal direction), the first drive circuit is adjacent to one second drive circuit in the second direction (see in Fig. 9 scan driving circuits SDC at the top left corner are adjacent to scan driving circuits SDC located at the lower left corner, in the vertical direction), and the third drive circuit is adjacent to another second drive circuit in the second direction (see in Fig. 9 scan driving circuits SDC at the top right corner are adjacent to other scan driving circuits SDC located at the lower right corner, in the vertical direction).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s invention, with the teachings in Min’s invention, to have the plurality of display partitions further comprises a third partition adjacent to the first partition in a first direction, wherein the second partition is located on a same side of the first partition and third partition in a second direction; and the first direction is intersected with the second direction; the plurality of drive circuits comprises one first drive circuit, two second drive circuits, and one third drive circuit, wherein the third drive circuit is configured to provide a gate drive signal to the plurality of sub-pixels within the third partition; and the two second drive circuits are located on two opposite sides of the second partition along the first direction, the first drive circuit is adjacent to the first partition in the first direction, the third drive circuit is adjacent to the third partition in the first direction, the first drive circuit is adjacent to one second drive circuit in the second direction, and the third drive circuit is adjacent to another second drive circuit in the second direction, for the advantage of a configuration that further provides reduction in non-display area (para[0006]).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), provided by the applicant on the record along with machine translation, in view of Min et al. (US 2022/0208929), as applied to claim 9 above, and further in view of Fu (CN109697966 A), provided by the applicant on the record along with machine translation.
Regarding claim 10, Zhu and Min disclose all the claim limitations as applied above (see claim 9). However, Zhu and Min do not appear to expressly disclose a second control circuit connected between the third drive circuit and a second drive circuit adjacent to the third drive circuit, wherein the second control circuit is configured to control display refresh frequencies of the second partition and the third partition to be the same or different.
Fu discloses a second control circuit connected between a third drive circuit and a second drive circuit adjacent to the third drive circuit, wherein the second control circuit is configured to control display refresh frequencies of a second partition and a third partition to be the same or different (see e.g. in Fig. 3, first switching unit 120 and second switch unit 130 connected between register group 110-1 (claimed third drive circuit) and register group 110-2 (claimed second drive circuit), to control refresh frequencies of a third partition connected to 110-1 and of a second partition connected to 110-2 to be the same or different; e.g. “In full display mode, the picture refresh frequency is normal”, “By controlling at least two first switch units 120 to be turned on at the same time, and controlling at least one second switch unit 130 to be turned off at the same time,… all shift register groups [110] can output drive signals step by step, so that the pixel array of the entire display area is scanned and the light-emitting state will be updated” and thus at the same frequency; also e.g. “In the partial area display mode, the picture refresh frequency is relatively high”, “By controlling at least two first switch units 120 to be turned off at the same lime, and controlling at least one second switch unit 130 to be turned on at the same time,… all even-numbered shift register groups [110] can output drive signals step by step, so that the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all even-numbered shift register groups 110 are scanned, and the luminous state will be updated, and the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all odd-numbered shift register groups 110 are not scanned, and the luminous state will not be updated, and the previous luminous state is maintained”, thus updating even and odd shift register groups 110 at different frequencies; para[0017]; para[0043]-para[0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s and Min’s combination, with the teachings in Fu’s invention, to have a second control circuit connected between the third drive circuit and a second drive circuit adjacent to the third drive circuit, wherein the second control circuit is configured to control display refresh frequencies of the second partition and the third partition to be the same or different, for the advantage of a configuration that reduces display unevenness and ghosting (para[0017]).
Regarding claim 11, Zhu, Min and Fu disclose all the claim limitations as applied above (see claim 10). In addition, Fu discloses the third drive circuit at least comprises a plurality of cascaded third scan control units, the second drive circuit at least comprises a plurality of cascaded second scan control units (see in Fig. 3 each shift register group 110 comprise cascaded shift registers 111; para[0009]); and
the second control circuit is configured to, under control of the first control line and a second control line, enable an output terminal of a last-stage third scan control unit of the third drive circuit and an input terminal of a first-stage second scan control unit of an second drive circuit adjacent to the third drive circuit to be connected, or enable a second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit adjacent to the third drive circuit to be connected (as shown in Fig. 3, under control of each line connected to each control end Ctr1 of each first switch unit 120 and to control end Ctr2 of second switch unit 130, commonly connected to line 160, an output terminal S2 of a last shift register 111 of e.g. register group 110-1 and an input terminal S1 of a first shift register 111 of register group 110-2 are connected, or a start signal line 152 and the input terminal S1 of the first shift register 111 of register group 110-2 are connected; para[0017]; para[0043]-para[0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the third drive circuit at least comprises a plurality of cascaded third scan control units; and the second drive circuit at least comprises a plurality of cascaded second scan control units; and the second control circuit is configured to, under control of the first control line and a second control line, enable an output terminal of a last-stage third scan control unit of the third drive circuit and an input terminal of a first-stage second scan control unit of an second drive circuit adjacent to the third drive circuit to be connected, or enable a second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit adjacent to the third drive circuit to be connected, as also taught by Fu, for the advantage of reducing a number of control signal lines, further narrow a border of the display panel, and further increase the screen-to-body ratio (para[0045]).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), provided by the applicant on the record along with machine translation, in view of Min et al. (US 2022/0208929), as applied to claim 9 above, and further in view of Xu et al. (US 2018/0366495).
Regarding claim 12, Zhu and Min disclose all the claim limitations as applied above (see claim 9). However, Zhu and Min do not appear to expressly disclose at least one third data line electrically connected with the plurality of sub-pixels within the third partition; wherein within the third partition, the at least one third data line is electrically connected with a second data auxiliary line through a second transfer line, an extension direction of the second transfer line is intersected with an extension direction of the second data auxiliary line, and the second data auxiliary line is extended to the second partition.
Xu discloses at least one third data line electrically connected with a plurality of sub-pixels within a third partition; wherein within the third partition, the at least one third data line is electrically connected with a second data auxiliary line through a second transfer line, an extension direction of the second transfer line is intersected with an extension direction of the second data auxiliary line, and the second data auxiliary line is extended to a second partition (regarding Figs. 1-4, the whole “display region A includes multiple sub-pixels P for image display” connected with data lines 122; within e.g. the upper half of the display array substrate in Fig. 1, at least one data line 122 is connected with an auxiliary data line 123 through connection wire 21, an extension direction of the connection wire 21 is intersected with an extension direction of the auxiliary data line 123, and the auxiliary data line 123 is extended to the lower half of the display array substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s and Min’s combination, with the teachings in Xu’s invention, to have at least one third data line electrically connected with the plurality of sub-pixels within the third partition; wherein within the third partition, the at least one third data line is electrically connected with a second data auxiliary line through a second transfer line, an extension direction of the second transfer line is intersected with an extension direction of the second data auxiliary line, and the second data auxiliary line is extended to the second partition, for the advantage of a narrow border design and improved display uniformity for display designs in which data lines conventional path is blocked (para[0019]).
Regarding claim 13, Zhu, Min and Xu disclose all the claim limitations as applied above (see claim 12). In addition, Xu discloses the second transfer line is located on a side of the second data auxiliary line close to the base substrate, and the second data auxiliary line and the third data line are in a same layer (regarding Figs. 2-3, see connection wire 21 is located on a side of the first auxiliary data line 123 close to a base substrate, and the first auxiliary data line 123 and the data line 122 are in a same layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the second transfer line is located on a side of the second data auxiliary line close to the base substrate, and the second data auxiliary line and the third data line are in a same layer, as also taught by Xu, for the advantage of achieving a display array substrate with narrow border design and improved display uniformity for display designs in which data lines conventional path is blocked (para[0014]; para[0017]; para[0019]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), in view of Fu (CN109697966 A), both provided by the applicant on the record along with corresponding machine translations, and Xu et al. (US 2018/0366495), as applied to claim 7 above, and further in view of Lee et al. (US 2021/0384229).
Regarding claim 14, Zhu, Fu and Xu disclose all the claim limitations as applied above (see claim 7). In addition, Xu discloses in a direction perpendicular to a display substrate, a display region comprises: a base substrate, a fifth conductive layer and sixth conductive layer that are disposed on the base substrate (regarding Figs. 2-3, see a base substrate and two conductive layers disposed on the base substrate); and the first transfer line is located the fifth conductive layer, and the first data auxiliary line, the first data line, and a second data line are located in the sixth conductive layer (regarding Figs. 2-3, see connection wires 21 located close to a base substrate, and the auxiliary data lines 123 and data lines 122 are in a same layer away from the base substrate).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have in a direction perpendicular to the display substrate, the display region comprises: a base substrate, a fifth conductive layer and sixth conductive layer that are disposed on the base substrate; and the first transfer line is located the fifth conductive layer, and the first data auxiliary line, the first data line, and a second data line are located in the sixth conductive layer, as also taught by Xu, for the advantage of achieving a display array substrate with narrow border design and improved display uniformity for display designs in which data lines conventional path is blocked (para[0014]; para[0017]; para[0019]).
However, the combination of Zhu, Fu and Xu do not appear to expressly disclose the display region comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer that are disposed on the base substrate.
Lee discloses in a direction perpendicular to a display substrate, a display region comprises: a base substrate (see 100 in Fig. 4), and a first semiconductor layer (see A1 in Fig. 4), a first conductive layer (see CE3 in Fig. 4), a second conductive layer (see G4a in Fig. 4), a second semiconductor layer (see A4 in Fig. 4), a third conductive layer (see G4b in Fig. 4), a fourth conductive layer (see 166 in Fig. 4) and a sixth conductive layer that are disposed on the base substrate (see 171 in Fig. 4); and a data line located in the sixth conductive layer (see data line 171 in the claimed sixth conductive layer, as shown in Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s, Fu’s and Xu’s, with the teachings in Lee’s invention, to have in a direction perpendicular to a display substrate, the display region comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer and sixth conductive layer that are disposed on the base substrate; the first transfer line is located in the fifth conductive layer, and the first data auxiliary line, the first data line, and the second data line are located in the sixth conductive layer, for the advantage of securing a display of high-quality characteristics such as low power consumption, high brightness, and high response speeds while securing transmission through a simple process (para[0003]; para[0180]).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), in view of Fu (CN109697966 A), both provided by the applicant on the record along with corresponding machine translations, in view of Xu et al. (US 2018/0366495), as applied to claim 7 above, and further in view of Asano et al. (US 2008/0024529).
Regarding claim 15, Zhu, Fu and Xu disclose all the claim limitations as applied above (see claim 7). However, Zhu, Fu and Xu do not appear to expressly disclose the sub-pixels comprise pixel circuits, and the display region comprises at least one pixel circuit group comprising two pixel circuits disposed adjacent to each other along a direction, wherein the two pixel circuits in the at least one pixel circuit group are disposed symmetrically with respect to a centerline of the pixel circuit group in the direction.
Asano discloses sub-pixels comprising pixel circuits (see pixel circuits 10 in Figs. 1 and 5), and a display region comprises at least one pixel circuit group comprising two pixel circuits disposed adjacent to each other along a direction, wherein the two pixel circuits in the at least one pixel circuit group are disposed symmetrically with respect to a centerline of the pixel circuit group in the direction (see e.g. in Figs. 1 and 5 pixel groups comprising two pixel circuits 10 adjacent to each other in a horizontal direction and symmetrically disposed with respect to a centerline O of the pixel group; para[0009]-para[0012]; para[0087]-para[0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s, Fu’s and Xu’s, with the teachings in Asano’s invention, to have the sub-pixels comprise pixel circuits, and the display region comprises at least one pixel circuit group comprising two pixel circuits disposed adjacent to each other along a direction, wherein the two pixel circuits in the at least one pixel circuit group are disposed symmetrically with respect to a centerline of the pixel circuit group in the direction, for the advantage of further reducing a layout area of pixel circuits for even higher definition (para[0009]-para[0012]).
Regarding claim 16, Zhu, Fu, Xu and Asano disclose all the claim limitations as applied above (see claim 15). In addition, Xu discloses the first data auxiliary line is located on a side of the data line, electrically connected with a pixel circuit of two pixel circuits, away from a first power supply line (regarding Figs. 1-2, see auxiliary data line 123 located on a side of a data line 122, connected to a pixel circuit of multiple pixel circuits, away from power lines; “The common electrodes and the pixel electrodes are located on a side of the data line”; para[0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the first data auxiliary line is located on a side of a data line, electrically connected with a pixel circuit of two pixel circuits, away from a first power supply line, as also taught by Xu, for the advantage of a narrow border design and improved display uniformity for display designs in which data lines conventional path is blocked (para[0019]).
In addition, Asano discloses the two pixel circuits in the at least one pixel circuit group are electrically connected with a same first power supply line, the first power supply line is located between data lines which are respectively electrically connected with the two pixel circuits (para[0009]-para[0012]; para[0087]-para[0088]; “power supply lines can be shared between the two pixel circuits”; e.g. the two pixel circuits 10 are connected to same power supply lines 26 or 27, and located between data lines 25 respectively connected to the two pixel circuits 10, as shown in Figs. 1 and 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the two pixel circuits in the at least one pixel circuit group are electrically connected with a same first power supply line, the first power supply line is located between data lines which are respectively electrically connected with the two pixel circuits, as also taught by Asano, and the first data auxiliary line is located on a side of the data line, electrically connected with a pixel circuit of the two pixel circuits, away from the first power supply line, as taught by the combination, for the advantage of reducing the number of power supply lines per pixel column, so that the layout area of the pixel circuits can be correspondingly reduced (para[0011]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN 207264753 U), in view of Fu (CN109697966 A), both provided by the applicant on the record along with corresponding machine translations, as applied to claim 19 above, and further in view of Min et al. (US 2022/0208929).
Regarding claim 20, Zhu and Fu disclose all the claim limitations as applied above (see claim 19). However, Zhu and Fu do not appear to expressly disclose the plurality of display partitions further comprises a third partition adjacent to the first partition in a first direction, the second partition is located on a same side of the first partition and the third partition in a second direction; and the first direction is intersected with the second direction, wherein providing, by the at least one drive circuit, the gate drive signal to the plurality of sub-pixels within the display partition corresponding to the at least one drive circuit further comprises: when display refresh frequencies of the second partition and the third partition are the same, a second control circuit enables an output terminal of a last-stage third scan control unit of a third drive circuit and an input terminal of a first-stage second scan control unit of a second drive circuit adjacent to the third drive circuit to be connected under control of the first control line and the second control line; and when the display refresh frequencies of the second partition and the third partition are different, the second control circuit enables the second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit adjacent to the third drive circuit to be connected under control of the first control line and the second control line.
Min discloses a plurality of display partitions further comprises a third partition adjacent to the first partition in a first direction, the second partition is located on a same side of the first partition and the third partition in a second direction (referring to Fig. 9, see e.g. pixels PX in the top right corner of the display area DA taken as comprising the claimed third partition adjacent, in a horizontal direction, to the pixels in the top left corner taken as comprising the claimed first partition, wherein the pixels at the lower portion of the display area DA are taken as the claimed second partition located on a same side of the claimed first partition and third partition in a vertical direction); and the first direction is intersected with the second direction (the horizontal and vertical directions intersected with each other, as shown in Fig. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhu’s and Fu’s invention, with the teachings in Min’s invention, to have the plurality of display partitions further comprises a third partition adjacent to the first partition in a first direction, the second partition is located on a same side of the first partition and the third partition in a second direction; and the first direction is intersected with the second direction, for the advantage of a configuration that further provides reduction in non-display area (see para[0006] of Min). Moreover, as a result of the combination and as already disclosed by Fu, the providing, by the at least one drive circuit, the gate drive signal to the plurality of sub-pixels within the display partition corresponding to the at least one drive circuit comprises: when display refresh frequencies of the second partition (the second partition connected to (even) register group 110-2 of Fig. 3 of Fu) and the third partition (e.g. a third partition also connected to (odd) register group 110-1 of Fig. 3 of Fu, in the combination) are the same, a second control circuit enables an output terminal of a last-stage third scan control unit of a third drive circuit and an input terminal of a first-stage second scan control unit of a second drive circuit adjacent to the third drive circuit to be connected under control of the first control line and the second control line (regarding Fu’s Fig. 3, see partitions connected to odd register groups and even partitions connected to even register groups; “In full display mode, the picture refresh frequency is normal”, “By controlling at least two first switch units 120 to be turned on at the same time, and controlling at least one second switch unit 130 to be turned off at the same time,… all shift register groups [110] can output drive signals step by step, so that the pixel array of the entire display area is scanned and the light-emitting state will be updated” and thus at the same frequency; accordingly, under control of each line connected to each control end Ctr1 of each first switch unit 120 and to control end Ctr2 of second switch unit 130, commonly connected to line 160, an output terminal S2 of a last shift register 111 of a register group 110 and an input terminal S1 of a first shift register 111 of a following register group below are connected; see para[0017], para[0043] and para[0047] of Fu); and when the display refresh frequencies of the second partition and the third partition are different, the second control circuit enables the second start signal line and the input terminal of the first-stage second scan control unit of the second drive circuit adjacent to the third drive circuit to be connected under control of the first control line and the second control line (regarding Fu’s Fig. 3, “In the partial area display mode, the picture refresh frequency is relatively high”, “By controlling at least two first switch units 120 to be turned off at the same lime, and controlling at least one second switch unit 130 to be turned on at the same time,… all even-numbered shift register groups [110] can output drive signals step by step, so that the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all even-numbered shift register groups 110 are scanned, and the luminous state will be updated, and the pixel units in the area corresponding to the drive signal lines 140 electrically connected to all odd-numbered shift register groups 110 are not scanned, and the luminous state will not be updated, and the previous luminous state is maintained”, thus updating even and odd shift register groups 110 at different frequencies; accordingly, under control of each line connected to each control end Ctr1 of each first switch unit 120 and to control end Ctr2 of second switch unit 130, commonly connected to line 160, the start signal line 152 and the input terminal S1 of the first shift register 111 of (even) register group 110-2 are connected; see para[0017], para[0043] and para[0047] of Fu). The combination provides the advantage of further reducing display unevenness and ghosting while reducing a number of control signal lines, thus narrowing a border of the display panel, and increasing the screen-to-body ratio (see para[0017]; para[0045] of Fu).
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623