DETAILED ACTION
It would be of great assistance to the Office if all incoming papers pertaining to a filed application carried the following items:
1. Application number (checked for accuracy, including series code and serial no.).
2. Group art unit number (copied from most recent Office communication).
3. Filing date.
4. Name of the examiner who prepared the most recent Office action.
5. Title of invention.
6. Confirmation number (See MPEP § 503).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 03/01/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden to examine Group I and Group II. This is found persuasive.
Status of Claims
Claims 4, 6, 11, 12, 16, 21, 24, 28 hand been canceled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 – 10, 17, 18 and 23 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the second initialization signal terminal" in line 17 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claims 6 – 10 and 17 are rejected based on their dependence on claim 5.
Claim 18 recites the limitation "the first initialization signal terminal" in line 5 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the second initialization signal terminal" in line 5 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the third initialization signal terminal" in line 6 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 23 recites the limitation "the first compensation control signal terminals" in line 18 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 13, 22, 25 and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng et al. (US 2016/0232840).
As to claim 1, Tseng discloses a pixel circuit, comprising:
a light-emitting device (OLED positioned between ELVSS and T_dri of fig. 11);
a driving transistor (T_dri of fig. 11) configured to generate a driving current for driving the light-emitting device (OLED positioned between ELVSS and T_dri of fig. 11) to emit light according to a data voltage (Data of fig. 11);
a coupling control circuit (C1 and C2 of fig. 11) coupled to a first node (node between T2 and C1 of fig. 11), and a gate electrode and a second electrode of the driving transistor (T_dri of fig. 11) and configured to stabilize voltages at the first node (node between T2 and C1 of fig. 11), and the gate electrode and the second electrode of the driving transistor (T_dri of fig. 11);
a signal writing circuit (circuit comprising T2 and T4 of fig. 11) coupled to the first node (node between T2 and C1 of fig. 11) and a first electrode of the driving transistor (T_dri of fig. 11) and configured to provide a signal from a data signal terminal (Data of fig. 11) to the first node (node between T2 and C1 of fig. 11) in response to a signal from a scan signal terminal (Sn_n of fig. 11), and to provide a signal from a first power terminal (ELVDD of fig. 11) to the first electrode of the driving transistor (T_dri of fig. 11) in response to a signal from a light-emitting control signal terminal (Em_n of fig. 11);
and a threshold compensation circuit (T3 of fig. 11 [0026], [0036]) coupled to the driving transistor (T_dri of fig. 11) and configured to write a threshold voltage (compensating transistor T3 is coupled to the driving transistor T_dri for compensating the threshold voltage Vth of the driving transistor T_dri [0026], [0036]) of the driving transistor (T_dri of fig. 11) to the gate electrode of the driving transistor (T_dri of fig. 11).
As to claim 2 (dependent on 1), Tseng discloses the pixel circuit, wherein
the coupling control circuit (C1 and C2 of fig. 11) comprises:
a first coupling control sub-circuit (C1 of fig. 11) and a second coupling control sub-circuit (C2 of fig. 11);
the first coupling control sub-circuit (C1 of fig. 11) is configured to stabilize the voltage at the gate electrode of the driving transistor (T_dri of fig. 11) and the voltage at the first node (node between T2 and C1 of fig. 11);
and the second coupling control sub-circuit (C2 of fig. 11) is configured to stabilize the voltage at the second electrode of the driving transistor (T_dri of fig. 11) and stabilize the voltage at the gate electrode of the driving transistor (T_dri of fig. 11) or the first node (node between T2 and C1 of fig. 11).
As to claim 3 (dependent on 2), Tseng discloses the pixel circuit, wherein
the first coupling control sub-circuit (C1 of fig. 11) comprises:
a first capacitor (C1 of fig. 11);
and a first plate of the first capacitor (C1 of fig. 11) is coupled to the gate electrode of the driving transistor (T_dri of fig. 11), and a second plate of the first capacitor (C1 of fig. 11) is coupled to the first node (node between T2 and C1 of fig. 11);
and the second coupling control sub-circuit (C2 of fig. 11) comprises:
a second capacitor (C2 of fig. 11);
and a first plate of the second capacitor (C2 of fig. 11) is coupled to the second electrode of the driving transistor (T_dri of fig. 11), and a second plate of the first capacitor (C1 of fig. 11) is coupled to the gate electrode of the driving transistor (T_dri of fig. 11) or the first node (node between T2 and C1 of fig. 11).
As to claim 13 (dependent on 2), Tseng discloses the pixel circuit, wherein
the signal writing circuit (circuit comprising T2 and T4 of fig. 11) comprises:
a fourth transistor (T2 of fig. 11) and a fifth transistor (T4 of fig. 11);
a gate electrode of the fourth transistor (T2 of fig. 11) is coupled to the scan signal terminal (Sn_n of fig. 11), a first electrode of the fourth transistor (T2 of fig. 11) is coupled to the data signal terminal (Data of fig. 11), and a second electrode of the fourth transistor (T2 of fig. 11) is coupled to the first node (node between T2 and C1 of fig. 11);
and a gate electrode of the fifth transistor (T4 of fig. 11) is coupled to the light-emitting control signal terminal (Em_n of fig. 11), a first electrode of the fifth transistor (T4 of fig. 11) is coupled to the first power terminal (ELVDD of fig. 11), and a second electrode of the fifth transistor (T4 of fig. 11) is coupled to the first electrode of the driving transistor (T_dri of fig. 11).
As to claim 22 (dependent on 1), Tseng discloses a display panel, comprising:
a plurality of sub-pixels (600 of fig. 5);
wherein
each of the plurality of sub-pixels comprises the pixel circuit of claim 1 (OLED display panel of fig. 5).
As to claim 25 (dependent on 22), Tseng discloses a display apparatus, comprising the display panel of claim 22 (OLED display panel 500 [0024] is also an apparatus).
As to claim 26 (dependent on 1), Tseng discloses a method for driving the pixel circuit, wherein
each of a plurality of consecutive display frames comprises an initialization stage (Reset of fig. 13), a threshold compensation stage (Comp of fig. 13), a data writing stage (Prog_N of fig. 13) and a luminescent stage (Emitting of fig. 13), and the method comprises:
in the initialization stage (Reset of fig. 13), providing, by the signal writing circuit (circuit comprising T2 and T4 of fig. 11), a signal from the first power terminal (ELVDD of fig. 11) to the first electrode of the driving transistor (T_dri of fig. 11) in response to a signal from the light-emitting control signal terminal (Em_n of fig. 11), and stabilizing, by the coupling control circuit (C1 and C2 of fig. 11), the voltages at the first node (node between T2 and C1 of fig. 11), the gate electrode and the second electrode of the driving transistor (T_dri of fig. 11);
in the threshold compensation stage (Comp of fig. 13), writing, by the threshold compensation circuit (T3 of fig. 11 [0026], [0036]), the threshold voltage of the driving transistor (T_dri of fig. 11) to the gate electrode of the driving transistor (T_dri of fig. 11), and stabilizing, by the coupling control circuit (C1 and C2 of fig. 11), the voltages at the first node (node between T2 and C1 of fig. 11), the gate electrode and the second electrode of the driving transistor (T_dri of fig. 11);
in the data writing stage (Prog_N of fig. 13), providing, by the signal writing circuit (circuit comprising T2 and T4 of fig. 11), a signal from the data signal terminal (Data of fig. 11) to the first node (node between T2 and C1 of fig. 11) in response to a signal from the scan signal terminal (Sn_n of fig. 11), and stabilizing, by the coupling control circuit (C1 and C2 of fig. 11), the voltages at the first node (node between T2 and C1 of fig. 11), the gate electrode and the second electrode of the driving transistor (T_dri of fig. 11);
and in the luminescent stage (Emitting of fig. 13), providing, by the signal writing circuit (circuit comprising T2 and T4 of fig. 11), a signal from the first power terminal (ELVDD of fig. 11) to the first electrode of the driving transistor (T_dri of fig. 11) in response to a signal from the light-emitting control signal terminal (Em_n of fig. 11), stabilizing, by the coupling control circuit (C1 and C2 of fig. 11), the voltages at the first node (node between T2 and C1 of fig. 11), the gate electrode and the second electrode of the driving transistor (T_dri of fig. 11), and generating, by the driving transistor (T_dri of fig. 11), a driving current for driving the light-emitting device (OLED positioned between ELVSS and T_dri of fig. 11) to emit light according to the data voltage (Data of fig. 11), to drive the light-emitting device (OLED positioned between ELVSS and T_dri of fig. 11) to emit light;
wherein
in each display frame, the voltage from the first power terminal is at a high level (ELVDD of fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tseng in view of Zou et al. (US 2019/0073955).
As to claim 14 (dependent on 1) and claim 15 (dependent on 14), Tseng discloses the pixel circuit, but does not explicitly disclose that the pixel circuit further comprises: a reset circuit; and the reset circuit is configured to provide a signal from a third initialization signal terminal to the second electrode of the driving transistor in response to a signal from a reset signal terminal; wherein the reset signal terminal and the scan signal terminal are a same signal terminal; and wherein the reset circuit comprises: a sixth transistor; and a gate electrode of the sixth transistor is coupled to the reset signal terminal, a first electrode of the sixth transistor is coupled to the third initialization signal terminal, and a second electrode of the sixth transistor is coupled to the second electrode of the driving transistor.
In the same filed of endeavor, Zou discloses a pixel driving circuit (TITLE), wherein
the pixel circuit (fig. 2) further comprises:
a reset circuit (reset circuit 60 of fig. 2);
and the reset circuit (reset circuit 60 of fig. 2) is configured to provide a signal from a third initialization signal terminal (VINT2 of fig. 2) to the second electrode of the driving transistor (DTFT of fig. 2 through MT5 of fig.2) in response to a signal from a reset signal terminal (G(n) of fig. 2); wherein
the reset signal terminal (G(n) of fig. 2) and the scan signal (G(n) of fig. 2) terminal are a same signal terminal (fig. 2, MT3 an dMT6 are driven by G(n));
and wherein
the reset circuit (60 of fig. 2) comprises:
a sixth transistor (MT6 of fig. 2);
and a gate electrode of the sixth transistor (MT6 of fig. 2) is coupled to the reset signal terminal (G(n) of fig. 2), a first electrode of the sixth transistor is coupled to the third initialization signal terminal (VINT2 of fig. 2), and a second electrode of the sixth transistor is coupled to the second electrode of the driving transistor (DTFT of fig. 2 through MT5 of fig.2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tseng and the teachings of Zou such that the reset circuit was provided as disclosed by Zou, with motivation to eliminate the afterimage of the OLED display device in a display process (Zou [0005]).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tseng in view of Zou et al. (US 2019/0073955).
As to claim 19 (dependent on 1) and claim 20 (dependent on 19), Tseng discloses the pixel circuit, but does not explicitly disclose the pixel circuit further comprises: an initialization circuit; and the initialization circuit is configured to provide a signal from a fourth initialization signal terminal to the gate electrode of the driving transistor in response to a signal from a fourth compensation control signal terminal; wherein the initialization circuit comprises: a seventh transistor; and a gate electrode of the seventh transistor is coupled to the fourth compensation control signal terminal, a first electrode of the seventh transistor is coupled to the fourth initialization signal terminal, and a second electrode of the seventh transistor is coupled to the gate electrode of the driving transistor; and wherein the fourth initialization signal terminal is a same signal terminal as the first power terminal.
In the same filed of endeavor, Yu disclose a pixel driving circuit (TITLE) comprising:
an initialization circuit (first reset sub-circuit 61 of fig. 6);
and the initialization circuit (first reset sub-circuit 61 of fig. 6) is configured to provide a signal from a fourth initialization signal terminal (VDD of fig. 6) to the gate electrode of the driving transistor (T3 of fig. 6) in response to a signal from a fourth compensation control signal terminal (RE of fig. 6); wherein
the initialization circuit (first reset sub-circuit 61 of fig. 6) comprises:
a seventh transistor (T1 of fig. 6);
and a gate electrode of the seventh transistor (T1 of fig. 6) is coupled to the fourth compensation control signal terminal (RE of fig. 6), a first electrode of the seventh transistor is coupled to the fourth initialization signal terminal (VDD of fig. 6), and a second electrode of the seventh transistor is coupled to the gate electrode of the driving transistor (T3 of fig. 6);
and wherein
the fourth initialization signal terminal (VDD of T1 fig. 6) is a same signal terminal as the first power terminal (VDD connected to T5 of fig. 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tseng and the teachings of Yu such that the initialization circuit was provided as disclosed by Yu, with motivation to improve brightness uniformity of an AMOLED display (Yu [0004]).
Allowable Subject Matter
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 27 (dependent on 26), Tseng discloses the driving method, comprising
the initialization stage (Reset of fig. 13), but Tseng alone or in combination with other art of record fails to disclose the driving method further comprises:
initializing, by the threshold compensation circuit, the first node and the gate electrode, the first electrode, and the second electrode of the driving transistor;
and there is a black frame insertion between any two adjacent ones of at least some of the plurality of display frames, and the method further comprises:
in the black frame insertion, providing, by the signal writing circuit, a signal from the first power terminal (to the first electrode of the driving transistor in response to a signal from the light-emitting control signal terminal;
initializing, by the threshold compensation circuit, the first node and the gate electrode, the first electrode, and the second electrode of the driving transistor;
and stabilizing, by the coupling control circuit, the voltages at the first node, the gate electrode and the second electrode of the driving transistor;
wherein
the voltage from the first power terminal is at a low level. (Emphasis Added.)
Conclusion
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/DMITRIY BOLOTIN/ Primary Examiner, Art Unit 2623
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