Prosecution Insights
Last updated: October 02, 2026
Application No. 18/857,967

IMPEDANCE MEASUREMENT APPARATUS AND IMPEDANCE MEASUREMENT METHOD

Non-Final OA §102§103
Filed
Oct 18, 2024
Priority
Apr 22, 2022 — JP 2022-070705 +1 more
Examiner
MCANDREW, CHRISTOPHER P
Art Unit
Tech Center
Assignee
Screen Holdings Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
850 granted / 989 resolved
+25.9% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
1011
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
50.5%
+10.5% vs TC avg
§102
28.4%
-11.6% vs TC avg
§112
15.8%
-24.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 989 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) & (a)(2) as being anticipated by Nakajima et al (Translation of WO 2020189172). Regarding Independent claim 1, Nakajima teaches: An impedance measurement apparatus (Paragraphs 0001, 0006-0010, 0072, & elsewhere.) comprising: a measurement container (Fig. 1 Element 10. Paragraphs 0001, 0006-0010, & 0027-0033.) (Paragraphs 0001, 0006-0010, & 0027-0033.); a plurality of first electrodes arranged in an array on a bottom surface of the measurement container (Fig. 2 Elements 8 & 81. Paragraphs 0036-0041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”); a second electrode and a third electrode that are located inside the measurement container (Fig. 2 Elements 8 & 82. Paragraphs 0036-00041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”); a voltage application circuit that applies a voltage between each of the first electrodes and the second electrode (Fig. 4 Element 31, the voltage application source. See paragraphs 0051-0054.); a current detection circuit that detects current flowing through each of the first electrodes (Fig. 1 Element 40. See paragraphs 0030, 0046, 0048, 0050, 0056, & elsewhere.); and a voltage detection circuit that detects a voltage between each of the first electrodes and the third electrode (Fig. 1 Element 30. See paragraphs 0030, 0045, 0048, & 0050-0051.). PNG media_image1.png 508 740 media_image1.png Greyscale PNG media_image2.png 398 446 media_image2.png Greyscale PNG media_image3.png 510 750 media_image3.png Greyscale Regarding claim 2, Nakajima teaches all elements of claim 1, upon which this claim depends. Nakajima teaches the third electrode is located on the bottom surface (Fig. 2 Elements 8 & 83. Paragraphs 0036-0041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”). Regarding claim 3, Nakajima teaches all elements of claim 1, upon which this claim depends. Nakajima teaches an electrode selection circuit that selects one first electrode that is to be connected to the current detection circuit, from among the plurality of first electrodes (Fig. 2 Elements 8 & 81. Paragraphs 0036-0041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 5 & 6 are rejected under 35 U.S.C. 103 as being unpatentable over Nakajima et al (Translation of WO 2020189172). Regarding claim 5, Nakajima teaches all elements of claim 1, upon which this claim depends. Nakajima does not explicitly teach a calculation unit that calculates an impedance in accordance with the current detected by the current detection circuit and the voltage detected by the voltage detection circuit. But it would have been obvious to one of ordinary skill in the art before the effective time of filing to have a calculation unit that calculates an impedance in accordance with the current detected by the current detection circuit and the voltage detected by the voltage detection circuit because all necessary variables are present to make this common, well-known calculation and because it would provide more and better information regarding the system. Regarding claim 6, Nakajima teaches: An impedance measurement method comprising: a) applying an alternating voltage between at least one of a plurality of first electrodes and a second electrode (Fig. 4 Element 31, the voltage application source. See paragraphs 0051-0054.), the plurality of first electrodes being arranged in an array on a bottom surface of a measurement container (Fig. 2 Elements 8 & 81. Paragraphs 0036-0041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”), the second electrode being located inside the measurement container (Fig. 2 Elements 8 & 821. Paragraphs 0036-0041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”); b) detecting current flowing through the first electrode(s) while the alternating voltage is applied (Fig. 1 Element 40. See paragraphs 0030, 0046, 0048, 0050, 0056, & elsewhere.) by the operation a); c) detecting a voltage between the first electrode(s) and a third electrode while the alternating voltage is applied (Fig. 1 Element 30. See paragraphs 0030, 0045, 0048, & 0050-0051.) by the operation a); and Nakajima does not explicitly teach: d) calculating an impedance of a target object in accordance with the current detected by the operation b) and the voltage detected by the operation c). But it would have been obvious to one of ordinary skill in the art before the effective time of filing to calculate an impedance of a target object in accordance with the current detected by the operation b) and the voltage detected by the operation c) because all necessary variables are present to make this common, well-known calculation and because it would provide more and better information regarding the system. Claims 5 & 6 are rejected, in the alternative, under 35 U.S.C. 103 as being unpatentable over Nakajima et al (Translation of WO 2020189172) in view of Renaud et al (U.S. PGPub # 2010/0006441). Regarding claim 5, Nakajima teaches all elements of claim 1, upon which this claim depends. Nakajima does not explicitly teach a calculation unit that calculates an impedance in accordance with the current detected by the current detection circuit and the voltage detected by the voltage detection circuit. Renaud teaches a calculation unit that calculates an impedance in accordance with the current detected by the current detection circuit and the voltage detected by the voltage detection circuit (Paragraph 0295.). It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Renaud to the teachings of Nakajima such that one would have a calculation unit that calculates an impedance in accordance with the current detected by the current detection circuit and the voltage detected by the voltage detection circuit because all necessary variables are present to make this common, well-known calculation and because it would provide more and better information regarding the system. Regarding claim 6, Nakajima teaches: An impedance measurement method comprising: a) applying an alternating voltage between at least one of a plurality of first electrodes and a second electrode (Fig. 4 Element 31, the voltage application source. See paragraphs 0051-0054.), the plurality of first electrodes being arranged in an array on a bottom surface of a measurement container (Fig. 2 Elements 8 & 81. Paragraphs 0036-0041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”), the second electrode being located inside the measurement container (Fig. 2 Elements 8 & 821. Paragraphs 0036-0041. Paragraph 0036 discloses “the electrode section 8 has a plurality of array electrodes 81, a plurality of peripheral electrodes 82, and an insertion electrode 83.”); b) detecting current flowing through the first electrode(s) while the alternating voltage is applied (Fig. 1 Element 40. See paragraphs 0030, 0046, 0048, 0050, 0056, & elsewhere.) by the operation a); c) detecting a voltage between the first electrode(s) and a third electrode while the alternating voltage is applied (Fig. 1 Element 30. See paragraphs 0030, 0045, 0048, & 0050-0051.) by the operation a); and Nakajima does not explicitly teach: d) calculating an impedance of a target object in accordance with the current detected by the operation b) and the voltage detected by the operation c). Renaud teaches: d) calculating an impedance of a target object in accordance with the current detected by the operation b) and the voltage detected by the operation c) (Paragraph 0295.). It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Renaud to the teachings of Nakajima such that one would have a calculation unit that calculates an impedance in accordance with the current detected by the current detection circuit and the voltage detected by the voltage detection circuit because all necessary variables are present to make this common, well-known calculation and because it would provide more and better information regarding the system. Allowable Subject Matter Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art listed does not anticipate alone or combine in an obvious manner to teach the invention claimed by applicant. The requirement to have a “differential-signal detection circuit that detects a difference between an alternating voltage applied by the voltage application circuit and a voltage output from the current detection circuit” is novel over the prior art of record. The technical effect of the difference is that the differential-signal detection circuit produces a coherent, phase-accurate comparison signal (Vy) that directly represents the difference between the applied AC excitation (Vs) and the current-derived voltage (R₂-i) generated by the current detection circuit. This limitation allows one “to reliably obtain the phase relationship between the applied (AC) excitation and the electrode current in order to calculate complex impedance with high accuracy.” Regarding claim 4, Nakajima teaches all elements of claim 1, upon which this claim depends. Nakajima teaches the current detection circuit is capable of outputting a voltage responsive to the current, the impedance measurement apparatus further comprising: a differential-signal detection circuit that detects a difference between an alternating voltage applied by the voltage application circuit and a voltage output from the current detection circuit. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art listed but not cited represents the previous state of the art and analogous art that teaches some of the limitations claimed by applicant. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER P MCANDREW whose telephone number is (469)295-9025. The examiner can normally be reached Monday-Thursday 6-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached on 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858
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Prosecution Timeline

Oct 18, 2024
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+13.9%)
2y 3m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 989 resolved cases by this examiner. Grant probability derived from career allowance rate.

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