Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 of U.S. Application 18/858,456 filed on October 21,2024 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/21/2024 and 11/25/2025 has been considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3, 6, 7, 9, 10, 11, 12, 15, and 16 are rejected under 35 U.S.C. 102(a1) as being unpatentable over Hirono et al (US Pat No. 9360515).
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Prior Art: Hirono
Regarding claim 1, Hirono discloses a method of detecting whether an inverter fails (abstract disclose fault detection for an inverter system), the method comprising: stopping an operation of the inverter (col 5 lines 49-61 discloses stops driving of the inverter); setting a plurality of pins (such as input outputs not fully shown) constituting a processor (30) as output ports or input ports; and detecting whether the inverter fails (disclosed in abstract to determine faults), based on an operation with respect to at least one pin set as an output port or an input port among the plurality of pins (col 5 lines 16-29 discloses applying second test voltage to determine if the inverter has failed. Therefore, the processor functions as both input and output).
Regarding claim 2, Hirono discloses wherein the detecting comprises identifying the operation with respect to the at least one pin set as the output port (col 5 lines 49-60 discloses applied current to the inverter).
Regarding claim 3, Hirono discloses wherein the detecting comprises: setting the at least one pin as the output port to generate an output signal (col 5 lines 49-60 discloses applied current to the inverter); converting the at least one pin set as the output port into an input port to receive an input signal corresponding to the output signal (to receive the signal to determine if a fault is determined); and comparing the output signal with the input signal to determine whether an error has occurred in the at least one pin (abstract and claim 1 discloses determining failure of the inverter based on the applied second test voltage. Therefore, the input and output are compared to determined fault that is sensed on the pin).
Regarding claim 6, Hirono discloses wherein the detecting comprises identifying the operation with respect to the at least one pin set as the input port (col 5 lines 35-49 discloses determining fault based on the second voltage. Therefore, is set to input).
Regarding claim 7, Hirono discloses wherein the detecting comprises: setting the at least one pin as the input port; and determining whether an error has occurred in the at least one pin, based on a signal received from a device connected to a terminal of the processor (col 5 lines 35-49 discloses determining fault based on the second voltage. Therefore, is set to input).
Regarding claim 9, Hirono discloses wherein a computer-readable recording medium having recorded thereon a program for causing a computer to execute the method (col 5 lines 20-29 discloses microprocessor known to be a programmable medium).
Regarding claim 10, Hirono discloses a processor (30) configured to: stop an operation of an inverter (col 5 lines 49-61 discloses stops driving of the inverter); set a plurality of pins (such as input outputs not fully shown) constituting a processor as output ports or input ports; and detect whether the inverter fails (disclosed in abstract to determine faults), based on an operation with respect to at least one pin set as an output port or an input port among the plurality of pins (col 5 lines 16-29 discloses applying second test voltage to determine if the inverter has failed. Therefore, the processor functions as both input and output).
Regarding claim 11, Hirono discloses wherein the processor is further configured to identify the operation with respect to the at least one pin set as the output port (col 5 lines 49-60 discloses applied current to the inverter).
Regarding claim 12, Hirono discloses wherein the processor is further configured to:set the at least one pin as the output port to generate an output signal (col 5 lines 49-60 discloses applied current to the inverter); convert the at least one pin set as the output port into an input port to receive an input signal corresponding to the output signal; and compare the output signal with the input signal to determine whether an error has occurred in the at least one pin (abstract and claim 1 discloses determining failure of the inverter based on the applied second test voltage. Therefore, the input and output are compared to determined fault that is sensed on the pin).
Regarding claim 15, Hirono discloses wherein the processor is further configured to identify the operation with respect to the at least one pin set as the input port (col 5 lines 35-49 discloses determining fault based on the second voltage. Therefore, is set to input).
Regarding claim 16, Hirono discloses wherein the processor is further configured to set the at least one pin as the input port and determine whether an error has occurred in the at least one pin, based on a signal received from a device connected to a terminal of the processor (col 5 lines 35-49 discloses determining fault based on the second voltage. Therefore, is set to input).
Allowable Subject Matter
Claims 4, 5, 8, 13, 14, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art of record taken alone or in combination fail to teach or suggest a method of detecting whether an inverter fails, the method comprising: wherein the detecting comprises detecting whether an error has occurred in the at least one pin by comparing an output signal generated from the at least one pin with an input signal received from the at least one pin due to a ground short in combination with the other limitations of the claim.
Claim 5 is also objected to as they depend on claim 4.
Regarding claim 8, the prior art of record taken alone or in combination fail to teach or suggest a method of detecting whether an inverter fails, the method comprising: wherein the detecting comprises: identifying a normal range of a signal strength corresponding to the device connected to the terminal; receiving a signal from the device connected to the terminal; and determining whether an error has occurred in the at least one pin, based on whether a strength of the received signal is within the normal range in combination with the other limitations of the claim.
Regarding claim 13, the prior art of record taken alone or in combination fail to teach or suggest a processor configured to: wherein the processor is further configured to detect whether an error has occurred in the at least one pin by comparing an output signal generated from the at least one pin with an input signal received from the at least one pin due to a ground short in combination with the other limitations of the claim.
Claim 14 is also objected to as they depend on claim 13.
Regarding claim 17, the prior art of record taken alone or in combination fail to teach or suggest a processor configured to wherein the processor is further configured to: identify a normal range of a signal strength corresponding to the device connected to the terminal; receive a signal from the device connected to the terminal; and determine whether an error has occurred in the at least one pin, based on whether a strength of the received signal is within the normal range in combination with the other limitations of the claim.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Figie et al (US Pat No 9899953): discloses ground fault at the output of an inverter section.
Shimana et al (USPGPub 20090284198): discloses abnormality in the inverter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOMINIC E HAWKINS whose telephone number is (571)272-2647. The examiner can normally be reached Monday-Friday 7:30am-5:00pm EST.
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/DOMINIC E HAWKINS/Primary Examiner, Art Unit 2858
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