DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 12 and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaeriyama (US 2017/0373676).
Regarding claims 1 and 12, Kaeriyama’s figures 3-4 shows a driving circuit for power semiconductor device TR, the driving circuit comprising a first gate voltage control circuit (a controller CTR, a plurality of registers REG to REGn, a selection circuit SEL, and a variable current driver circuit IDVC) to control a gate voltage of the power semiconductor element in response to a turn-on command of the power semiconductor element(turn-on instruction TON (corresponding to ”a turn-on command”), in a first tiem region (a current Il is generated by a register REG] during a period of STl (figures 4 and 5A corresponding to "a first time region”), and a current I2a is generated by a register REG2a (corresponding to ”a second time region”) during a period of ST2a (figure 14A) is generated by a register REG2b during a period of ST2b (figure 14A, corresponding to "a third time region”) in different manners, the gate voltage reaching the mirror voltage in the second time region or the third time region according to magnitude of a main current flowing through the power semiconductor element (according to a), collector-emitter current Ice, and a Miller plateau period in which a gate-emitter voltage Vge becomes substantially flat is entered), the driving circuit further comprising a second gate voltage control circuit to control the gate voltage greater than or equal to the mirror voltage ( the inter-emitter voltage Vge is increased by the register REG3 (corresponding to the ”second gate voltage control circuit”) during the period of ST3) as called for in claim 1.
Regarding claim 2, The driving circuit for a power semiconductor element according to claim 1, wherein the first gate voltage control circuit is configured to: increase the gate voltage to a first voltage at a first slope in the first time region (slope of Vge in ST1 time region); increase the gate voltage from the first voltage at a second slope gentler than the first slope in the second time region (ST2a slope in the second time region) ; and increase the gate voltage to the mirror voltage at a third slope (ST2b) gentler than the first slope and steeper than second slope in the third time region when the gate voltage has not reached the mirror voltage in the second time region, and the second gate voltage control circuit is configured to increase the gate voltage from the mirror voltage at a fourth slope steeper than the third slope (ST3).
Regarding claim 13, A method of driving a power semiconductor element, the method comprising: increasing a gate voltage of the power semiconductor element to a first voltage at a first slope in a first time region after receipt of a turn-on command of the power semiconductor element (slope of Vge in ST1 time region); increasing the gate voltage from the first voltage at a second slope gentler than the first slope in a second time region following the first time region (ST2a slope in the second time region); increasing, when the gate voltage has not reached a mirror voltage in the second time region, the gate voltage to the mirror voltage at a third slope (ST2b) gentler than the first slope and steeper than the second slope in a third time region following the second time region; and increasing the gate voltage from the mirror voltage at a fourth slope (ST3) steeper than the third slope.
Regarding claim 14, wherein increasing the gate voltage from the mirror voltage at the fourth slope (ST3) is performed when a predetermined period has elapsed since receipt of the turn- on command (TON).
Allowable Subject Matter
Claims 3-11 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2842 1/10/2026