Prosecution Insights
Last updated: August 17, 2026
Application No. 18/859,106

SSB HOPPING FOR COVERAGE EXTENSION

Non-Final OA §102§103
Filed
Oct 22, 2024
Priority
Jul 07, 2022 — IL 294583 +1 more
Examiner
GEORGE, AYANAH S
Art Unit
Tech Center
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
448 granted / 516 resolved
+26.8% vs TC avg
Moderate +6% lift
Without
With
+5.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
549
Total Applications
across all art units

Statute-Specific Performance

§101
4.0%
-36.0% vs TC avg
§103
61.4%
+21.4% vs TC avg
§102
20.8%
-19.2% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 516 resolved cases

Office Action

§102 §103
DETAILED ACTION This action is a response to an application filed on 10/22/24 in which claims 1-30 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 14-17, 23-27 and 30 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Axnas et al. (WO 2016/064315 A1), herein Axnas. As to claim 14, Axnas teaches an apparatus for wireless communication at a network entity, comprising: a memory (Axnas Fig. 11 memory); and at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to (Axnas Fig. 11 processor circuit): output one or more synchronization signal blocks (SSBs) based on a frequency hopping pattern (Axnas [0066] Referring now to Figure 8, systems/methods according to some embodiments may determine a frequency domain hopping pattern (block 130), generate synchronization signals based on the frequency domain hopping pattern (block 132), and transmit the synchronization signals (block 134)) ; and establish a connection with at least one user equipment (UE) that has detected a first SSB based on the frequency hopping pattern (Axanas [0002] [0002] In order for two nodes in a radio communication system to establish a connection with each other, they need to be synchronized (aligned) in time and frequency. Such synchronization is typically achieved by having one of the nodes, e.g. an access node (AN), transmit synchronization pilot symbols, or pilots, which comprise a set of predefined signals on predefined radio resources and [0075] Referring to Figure 13, a network node, such as a UE, may receive one or more synchronization signals (block 150). The node may analyze the received synchronization signals to determine the synchronization signal transmission pattern. For example, the node may analyze the received synchronization signals to determine the sequence generator used to generate the synchronization signal transmission pattern. In some embodiments, the node may analyze the received synchronization signals to determine the identity of a pseudorandom sequence generating function and/or seed used to generate the synchronization signal transmission pattern. Once the node determines the synchronization signal transmission pattern, the node proceeds to receive synchronization signals according to the determined synchronization signal pattern (block 154)) As to claim 27, Axnas teaches an method of wireless communication at a network entity, comprising: outputting one or more synchronization signal blocks (SSBs) based on a frequency hopping pattern (Axnas [0066] Referring now to Figure 8, systems/methods according to some embodiments may determine a frequency domain hopping pattern (block 130), generate synchronization signals based on the frequency domain hopping pattern (block 132), and transmit the synchronization signals (block 134)) and establishing a connection with at least one user equipment (UE) that has detected a first SSB based on the frequency hopping pattern (Axanas [0002] [0002] In order for two nodes in a radio communication system to establish a connection with each other, they need to be synchronized (aligned) in time and frequency. Such synchronization is typically achieved by having one of the nodes, e.g. an access node (AN), transmit synchronization pilot symbols, or pilots, which comprise a set of predefined signals on predefined radio resources and [0075] Referring to Figure 13, a network node, such as a UE, may receive one or more synchronization signals (block 150). The node may analyze the received synchronization signals to determine the synchronization signal transmission pattern. For example, the node may analyze the received synchronization signals to determine the sequence generator used to generate the synchronization signal transmission pattern. In some embodiments, the node may analyze the received synchronization signals to determine the identity of a pseudorandom sequence generating function and/or seed used to generate the synchronization signal transmission pattern. Once the node determines the synchronization signal transmission pattern, the node proceeds to receive synchronization signals according to the determined synchronization signal pattern (block 154)) As to claim 15, Axnas teaches the apparatus of claim 14, further comprising a transceiver coupled to the at least one processor (Axnas Fig. 11 transceiver) As to claim 16, Axnas teaches the apparatus of claim 14, wherein a first frequency of the first SSB is different from at least a second frequency of a second SSB (Axnas [0042] At each sync signal interval, a synchronization signal is transmitted on a frequency that changes from one sync signal interval to the next) As to claim 17, Axnas teaches the apparatus of claim 16, wherein the first SSB and the second SSB are comprised within a same or different frequency rasters (Axnas [0042] At each sync signal interval, a synchronization signal is transmitted on a frequency that changes from one sync signal interval to the next) As to claim 21, Axnas teaches the apparatus of claim 14, wherein the one or more SSBs comprise a frequency hopping indicator, wherein the frequency hopping indicator indicates the frequency hopping pattern, wherein the frequency hopping pattern is adjusted to comprise an increased or a decreased frequency hopping pattern (Axnas [0042] he hopping pattern may be provided so that the sync signals have an equal probability of falling within each defined frequency in an allowed bandwidth.) As to claim 23, Axnas teaches the apparatus of claim 14, wherein the one or more SSBs comprises a group of SSBs (Axnas [0042] At each sync signal interval, a synchronization signal is transmitted on a frequency that changes from one sync signal interval to the next) As to claim 24, Axnas teaches the apparatus of claim 23, wherein the group of SSBs are configured to hop together based on the frequency hopping pattern (Axnas [0056] Figure 3B illustrates time domain hopping of a synchronization signal according to further embodiments. As illustrated in Figure 3B, pairs of successive synchronization signals may be transmitted with the same time offset relative to the pilot grid, after which the time offset value may change in a pseudorandom or nonrandom manner) As to claim 25, Axnas teaches the apparatus of claim 23, wherein each SSB within the group of SSBs are configured to hop in a different frequency hopping pattern (Axnas [0056] Figure 3B illustrates time domain hopping of a synchronization signal according to further embodiments. As illustrated in Figure 3B, pairs of successive synchronization signals may be transmitted with the same time offset relative to the pilot grid, after which the time offset value may change in a pseudorandom or nonrandom manner) As to claim 26, Axnas teaches the apparatus of claim 14, wherein the at least one processor is further configured to: output a frequency hopping pattern indication that identifies the frequency hopping pattern, in response to the connection established with the at least one UE (Axnas [0063] The receiver may listen for synchronization signals and, when they are detected, determine the identity of the generating function and the seed in response to the received synchronization signals) Claim 30 is rejected for the same reasons stated in claim 26. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18-20, 28 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Axnas and Lee et al. (Pub. No.: 2022/0131656 A1), herein Lee. As to claim 18, Axnas teaches the apparatus of claim 14, Axnas does not teach wherein the at least one processor is further configured to: obtain an indication identifying a preferred SSB from the one or more SSBs. However Lee does teach wherein the at least one processor is further configured to: obtain an indication identifying a preferred SSB from the one or more SSBs (Lee [0250] the DCI of the PDSCH for the SSB index/CSI-RS resource/TCI state having the best measurement quality among the associated SSB index or CSI-RS resource or TCI states may be preferentially selected) It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Axnas and Lee, because Lee teaches us this may be considered to determine whether to perform HARQ Feedback (Lee [0250]) Claim 28 is rejected for the same reasons stated in claim 18. As to claim 19, the combination of Axnas and Lee teach the apparatus of claim 18, wherein the preferred SSB has a highest quality for the UE from the one or more SSBs (Lee [0250] the DCI of the PDSCH for the SSB index/CSI-RS resource/TCI state having the best measurement quality among the associated SSB index or CSI-RS resource or TCI states may be preferentially selected) It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Axnas and Lee for the same reasons stated in claim 18. As to claim 20, the combination of Axnas and Lee teach the apparatus of claim 18, wherein the at least one processor is further configured to: allocate one or more physical downlink shared channel (PDSCH) slots near the preferred SSB (Lee [0250] the DCI of the PDSCH for the SSB index/CSI-RS resource/TCI state having the best measurement quality among the associated SSB index or CSI-RS resource or TCI states may be preferentially selected) It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Axnas and Lee for the same reasons stated in claim 18. Claim 29 is rejected for the same reasons stated in claim 20. Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Axnas and Wang et al. (WO 2020/199069 A1), herein Wang. As to claim 22, Axnas teaches the apparatus of claim 14, Axnas does not teach wherein the at least one processor is further configured to: output a system information block type 1 (SIB 1) comprising a hop indication indicating a number of hops within a frequency hopping pattern of an SSB periodicity. However Wang does teach wherein the at least one processor is further configured to: output a system information block type 1 (SIB 1) comprising a hop indication indicating a number of hops within a frequency hopping pattern of an SSB periodicity (Wang page 6 lines 26-33 Among them, the first device may obtain the frequency hopping switch, frequency hopping period, and frequency hopping formula from the system information of the cell or sub-cell that it accesses, such as system information block (SIB), to determine the frequency hopping pattern Therefore, it is possible to determine whether to perform frequency hopping transmission according to the frequency hopping switch, and determine the carrier frequency used for transmission after each frequency hopping from the set of available frequency hopping carriers according to the frequency hopping formula, thereby generating a frequency hopping pattern) It would have been obvious before the effective filing date of the claimed invention to combine the teachings of Axnas with Wang, because Wang (page 7 lines 3-9) teaches us Since the second device accesses the sub-cell of the first device, it needs to use the same frequency hopping pattern as the first device for frequency hopping transmission. Therefore, in order for the second device to obtain the frequency hopping pattern of the sub-cell, the second device obtains information such as the set of frequency hopping carriers and the set of available frequency hopping carriers required to generate the frequency hopping pattern. Allowable Subject Matter Claims 1-13 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYANAH S GEORGE whose telephone number is (571)272-8880. The examiner can normally be reached 7:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hassan Phillips can be reached at 572-272-3940. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AYANAH S. GEORGE Primary Examiner Art Unit 2467 /AYANAH S GEORGE/Primary Examiner, Art Unit 2467
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Prosecution Timeline

Oct 22, 2024
Application Filed
Aug 06, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+5.9%)
2y 4m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 516 resolved cases by this examiner. Grant probability derived from career allowance rate.

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