DETAILED ACTION
This is in response to the application filed on October 23, 2024 in which claims 28 – 47 are presented for examination after preliminary amendment.
Status of Claims
Claims 28 – 47 are pending, of which claims 28, 35, 40, and 44 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: Applicant’s PGPub 2025/0284647 at [0269], [0276], [0284] states “For this example, a second portion of the range of memory addresses may be included in a second memory address of the memory at the second device.” This appears to be a typo. In other words, it is unclear how a range of memory addresses is included in a memory address. The examiner recommends amending the specification to state “For this example, a second memory address may be included in a second portion of the range of memory addresses
Appropriate correction is required.
Claim Objections
Claims 31 and 38 are objected to because of the following informalities: Claim 31 states “a second portion of the range of memory addresses is included in a second memory address of the memory at the second device.” The examiner recommends amending claims 31 and 38 to state “a second memory address is included in a second portion of the range of memory addresses Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 28, 29, 34 – 36, and 44 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duncan et al., U.S. Patent Application 2020/0159669 (hereinafter referred to as Duncan).
Referring to claim 28, Duncan discloses “An apparatus comprising: circuitry at a first device coupled with a host compute device” (Fig. 5B parallel processing unit PPU 300 and Fig. 3 PPU 300 including circuitry), “the circuitry to: determine whether a memory request received via a first link coupled with the host compute device” (Figs. 3, 5B, and 5C along with [0073] link 302 connects PPU to host. [0052] memory access request may comprise a read request, a write request, etc.) “includes a memory address to access a memory at the first device or includes a memory address to access a memory at a second device coupled with the first device via a second link included in a multi die fabric” ([0052] memory access request may comprise a read request, a write request, etc. Figs. 1A and 1B Fabric Linear Address (FLA) space 100 and [0019] “to provide a global virtual address space into which different processing nodes may uniquely map one or more ranges of local physical memory. In this way, shared local physical memory at a given processing node may be accessed by any other processing node or nodes through distinct and manageable address ranges within the FLA space.” [0034] “first local virtual address range 104(0) may be associated with physical memory residing at a first processing node 106(0), and second local virtual address range 104(1) may be associated with a physical memory residing at a second processing node 106(1) of a multiprocessor system.” [0036] “The processing nodes 106 may be configured to communicate access requests through a switching fabric.” [0113] – [0114] NVLinks may be an on-chip or on-die interconnect and “integrated circuit fabricated on a die or chip”); “cause a memory access to the memory address of the memory at the first device or the second device based on the determination” ([0004] “generating a memory access request comprising a virtual address (VA) within the virtual address space that targets data residing in the one or more local system physical memory pages, mapping the VA to a corresponding FLA within the FLA space that targets the data, composing a remote access request that includes the FLA, and transmitting the remote access request to the destination node” and [0035] “multiple different processing nodes 106 may export local memory for other processing nodes 106 to access, as well as access remote memory on other processing nodes 106 using a common address space defined by the FLA space 100”); “and send a response to the host compute device via the first link to indicate a status of the memory access to the memory address” ([0052] memory access request may comprise a read request, a write request, etc. [0079] results can be transmitted to another PPU or CPU. Fig. 5B and [0116] CPU access to each PPU’s memory, data read from the memories to be stored in the cache hierarchy of the CPU).
As per claim 29, Duncan discloses “the circuitry to determine whether the memory request includes a memory address to access the memory at the first device or includes a memory address to access the memory at the second device based on a forwarding table maintained at the first device, the forwarding table to include entries that indicate whether the memory address included in the memory request is to the memory at the first device or is to the memory at the second device” ([0042] source node configures one or more page table entries within a local TLB to map a virtual address space for the source node to the FLA space. [0043] “virtual address space that targets data residing in the one or more local system physical memory pages” and “the source node composes a remote access request that includes the FLA. In an embodiment, the FLA is within a specific FLA range 102, which is mapped to the destination node (i.e., a specific processing node 106).” [0055] “page table entries (PTEs) for the GPU MMUs 141 each include a field that indicates whether a corresponding virtual address range maps to local system physical memory or to an FLA (remote system physical memory)”).
As per claim 34, Duncan discloses “compute circuitry that includes a graphics processing unit” (Fig. 6 and [0018] a graphics processing pipeline implemented by the PPU of FIG. 3).
Referring to claim 35, claim 28 recites the corresponding limitations as that of claim 35. Therefore, the rejection of claim 28 applies to claim 35.
Note, claim 36 recites the corresponding limitations of claim 29. Therefore, the rejection of claim 29 applies to claim 36.
Referring to claim 44, Duncan discloses “At least one non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed by a system at a host compute device cause the system to” ([0005] and claim 21 computer readable medium storing instructions executed by a multiprocessor system): “receive a request to access a memory address of a memory at a first device from among a plurality of devices coupled with the host compute device via separate host links” (Fig. 5B 302, [0052] memory access request may comprise a read request, a write request, etc.); “obtain memory address mapping information to determine how to split the memory address into multiple portions that include at least a first portion and a second portion; send the first portion of the memory address to the first device in a first memory request message via a first host link to access the first portion of the memory address of the memory at the first device; and send, in a second memory request via a second host link, the second portion of the memory address to a second device from among the plurality of devices” (Fig. 1A FLA ranges 102 and nodes 106. [0047] [0047] local TLB and second TLB within a destination node, TLB includes a field to indicate whether a virtual address maps to a local memory device or to a remote memory device), “the second memory request to be forwarded to the first device via a first high speed internal-connect link (HSIL) to access the second portion of the memory address of the memory at the first device” (Fig. 5B NVLink 310. [0042] source node configures one or more page table entries within a local TLB to map a virtual address space for the source node to the FLA space. [0043] “virtual address space that targets data residing in the one or more local system physical memory pages” and “the source node composes a remote access request that includes the FLA. In an embodiment, the FLA is within a specific FLA range 102, which is mapped to the destination node (i.e., a specific processing node 106).” [0055] “page table entries (PTEs) for the GPU MMUs 141 each include a field that indicates whether a corresponding virtual address range maps to local system physical memory or to an FLA (remote system physical memory)”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 30, 31, 37, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Duncan in view of Meyer et al., U.S. Patent Application 2017/0168954 (hereinafter referred to as Meyer).
As per claim 30, Duncan discloses “the circuitry to: determine the memory request includes a memory address to access the memory at the second device” and ; coupling to “the second device via a second link coupled with the second device” (Fig. 5B NVLinks 310 coupling PPUs 300. [0055] “page table entries (PTEs) for the GPU MMUs 141 each include a field that indicates whether a corresponding virtual address range maps to local system physical memory or to an FLA (remote system physical memory).” [0092] transferring between multiple PPUs); and “the response sent to the host compute device in order to indicate a status of the access to the memory address of the memory at the second device” ([0052] memory access request may comprise a read request, a write request, etc. [0079] results can be transmitted to another PPU or CPU. Fig. 5B and [0116] CPU access to each PPU’s memory, data read from the memories to be stored in the cache hierarchy of the CPU).
Duncan does not appear to explicitly disclose “forward the memory request to the second device via a second link coupled with the second device; receive a response, via the second link, to the memory request from the second device; and include the response from the second device in the response sent to the host compute device.”
However, Meyer discloses “forward the memory request to the second device via a second link coupled with the second device; receive a response, via the second link, to the memory request from the second device; and include the response from the second device in the response” “in order to indicate a status of the access to the memory address of the memory at the second device” (Fig. 7 and [0049] a read request (RD_A) is sent to the SAM within RN-F0, the target can be a local-connection node on the same chip or a remote-connection node if the target is on another chip. [0053] updated request is sent to chip 1 at 718, [0055] when requested data is ready to be sent, a response is sent at 732. [0056] – [0057] the response is forwarded).
Duncan and Meyer are analogous art because they are from the same field of endeavor, which is remote memory access methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Duncan and Meyer before him or her, to modify the teachings of Duncan to include the teachings of Meyer so that a device forwards a memory request to another device based on address and forwards a response as well.
The motivation for doing so would have been to provide a means for having a single home node service requests for access to a large group of system memory addresses (as stated by Meyer at [0032]), with the home node acting as an interface block to other chips in the system (as stated by Meyer at [0024]).
Therefore, it would have been obvious to combine Meyer with Duncan to obtain the invention as specified in the instant claim.
As per claim 31, Duncan discloses “the second device to receive a second memory request from the host compute device via a second link coupled between the second device and the host compute device, the second memory request to include a request to access the second memory address” (Fig. 5C and [0034] “first local virtual address range 104(0) may be associated with physical memory residing at a first processing node 106(0), and second local virtual address range 104(1) may be associated with a physical memory residing at a second processing node 106(1) of a multiprocessor system.” [0052] the memory access request may be a read request, a write request, etc.).
As above, Applicant’s claim language is confusing regarding an address comprising a range of addresses.
However, Duncan discloses “the memory address of the memory at the second device comprises a first portion of a range of memory addresses of the memory at the second device, wherein a second portion of the range of memory addresses is included in a second memory address of the memory at the second device” (Fig. 1A and [0034] a first FLA range 102(0) and a second FLA range 102(1) within the FLA space 100).
Also, Meyer discloses “the memory address of the memory at the second device comprises a first portion of a range of memory addresses of the memory at the second device, wherein a second portion of the range of memory addresses is included in a second memory address of the memory at the second device” (Fig. 3A and Fig. 3B blocks of addresses and associated chips).
Note, claim 37 recites the corresponding limitations of claim 30. Therefore, the rejection of claim 30 applies to claim 37.
Note, claim 38 recites the corresponding limitations of claim 31. Therefore, the rejection of claim 31 applies to claim 38.
Claims 32, 33, 39 – 42, and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Duncan in view of ‘Compute Express Link (CXL) Specification, Revision 2.0’ (hereinafter referred to as CXL Spec).
As per claim 32, Duncan discloses “the first link comprises a” PCIe “link and the second link included in the multi die fabric is a high speed internal-connect link having a data bandwidth of at least 5 times a data bandwidth of the” PCIe “link” ([0073] interconnect 302 is a PCIe bus and Figs. 5B, 5C NVLink 310. Applicant describes PCIe at [0041] of Applicant’s PGPub 2025/0284647 as having a bandwidth of approximately 128 GB/sec and HSILs as having a bandwidth of approximately 500 GB/sec or more. Applicant describes NVLink at [0003] of Applicant’s PGPub 2025/0284647 as having a bandwidth of 500 GB/sec or more).
Duncan does not appear to explicitly disclose utilizing CXL links. As such, Duncan does not appear to explicitly disclose “the first link comprises a Compute Express Link (CXL) link and the second link included in the multi die fabric is a high speed internal-connect link having a data bandwidth of at least 5 times a data bandwidth of the CXL link.”
However, as stated by Applicant at [0042] of Applicant’s PGPub 2025/0284647, CXL links operate according to the PCIe specification.
Further, CXL Spec teaches that “CXL is a dynamic multi-protocol technology designed to support accelerators and memory devices,” “A key benefit of CXL is that it provides a low-latency, high-bandwidth path for an accelerator to access the system and for the system to access the memory attached to the CXL device,” and “CXL protocol is compatible with PCIe” (section 1.4.1).
It would have been obvious to one of ordinary skill in the art to utilize CXL links in place of PCIe links in the system of Duncan.
Duncan and CXL Spec are analogous art because they are from the same field of endeavor, which is remote memory access methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Duncan and CXL Spec before him or her, to modify the teachings of Duncan to include the teachings of CXL Spec so that the first link comprises a Compute Express Link (CXL) link and the second link included in the multi die fabric is a high speed internal-connect link having a data bandwidth of at least 5 times a data bandwidth of the CXL link.
The motivation for doing so would have been to provide a means for a low-latency, high-bandwidth path for an accelerator to access the system and for the system to access the memory attached to the CXL device (as stated by CXL Spec at 1.4.1).
Therefore, it would have been obvious to combine CXL Spec with Duncan to obtain the invention as specified in the instant claim.
As per claim 33, Duncan discloses “the memory at the first device comprises a first” high-bandwidth memory (HBM)” and the memory at the second device comprises a second” HBM (Fig. 3 and [0071] HBM. Also, Figs. 5B, 5C multiple PPUs, each with attached memory 304).
Duncan does not appear to explicitly disclose “a first host-managed device memory (HDM) and the memory at the second device comprises a second HDM.”
However, CXL Spec discloses “host-managed device memory (HDM)” (Table 1 on page 28 “Host-managed Device Memory” - Memory located on a CXL device can either be mapped as HDM or PDM. Section 2.2 and Figure 10 Type 2 CXL devices have high bandwidth memory (HBM) attached to the device and used as ‘Host-managed Device Memory (HDM)).
Duncan and CXL Spec are analogous art because they are from the same field of endeavor, which is remote memory access methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Duncan and CXL Spec before him or her, to modify the teachings of Duncan to include the teachings of CXL Spec so that the memory at the first device comprises a first host-managed device memory (HDM) and the memory at the second device comprises a second HDM.
The motivation for doing so would have been to provide a means for the host to access the memory attached to the CXL device without adding software and hardware cost (as stated by CXL Spec at section 2.2).
Therefore, it would have been obvious to combine CXL Spec with Duncan to obtain the invention as specified in the instant claim.
Note, claim 39 recites the corresponding limitations of claims 32 and 33. Therefore, the rejections of claims 32 and 33 applies to claim 39.
Referring to claim 40, Duncan discloses “At least one non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed by a system at a host compute device cause the system to” ([0005] and claim 21 computer readable medium storing instructions executed by a multiprocessor system) perform a method, “a plurality of devices coupled with the host compute device via separate host links” (Fig. 5B 302 and [0073] link 302 connects PPU to host); “access, via the host links,” “each device” (Fig. 5B 302 and [0073] link 302 connects PPU to host) and “to route a memory request received via a host link to other devices of the plurality of devices” ([0052] memory access request may comprise a read request, a write request, etc. [0042] source node configures one or more page table entries within a local TLB to map a virtual address space for the source node to the FLA space. [0043] “virtual address space that targets data residing in the one or more local system physical memory pages” and “the source node composes a remote access request that includes the FLA. In an embodiment, the FLA is within a specific FLA range 102, which is mapped to the destination node (i.e., a specific processing node 106).” [0055] “page table entries (PTEs) for the GPU MMUs 141 each include a field that indicates whether a corresponding virtual address range maps to local system physical memory or to an FLA (remote system physical memory)”), “the memory request to be routed via one of multiple high speed internal-connect links (HSILs) that couple the plurality of devices together” (Fig. 5B NVLink 310 and [0047] TLB includes a field to indicate whether a virtual address maps to a local memory device or to a remote memory device); “build a system memory address mapping”, “the system memory address mapping for use by the host compute device to access a memory address for memory at a respective device from among the plurality of devices” (Fig. 1A Fabric Linear Address (FLA) space, [0004] configuring to map a virtual address space for the source node to the FLA space, and [0042] at least one FLA range of the FLA space is mapped to one or more local system physical memory pages comprising a local system physical address (SPA) space for a memory subsystem of the destination node); “and cause separate forwarding tables to be maintained at each device from among the plurality of devices” ([0047] local TLB and second TLB within a destination node, TLB includes a field to indicate whether a virtual address maps to a local memory device or to a remote memory device), “the memory request received via a host link coupled with the host compute device and forwarded to the other device via an HSIL based on the device's forwarding table” (Fig. 5B link 302, [0047] TLB includes a field to indicate whether a virtual address maps to a local memory device or to a remote memory device, and Fig. 5B NVLink 310).
Duncan does not appear to explicitly disclose “initialize a plurality of devices coupled with the host,” “access, via the host links, registers at each device to gather information on a device's capability to route a memory request received,” “build a system memory address mapping based on the gathered information,” and “the separate forwarding tables to indicate a device's capability to route a memory request to access a memory address of a memory at another device from among the plurality of devices.”
However, CXL Spec discloses “initialize a plurality of devices coupled with the host” (section 8.1.3 page 259 CXL 2.0 device is enumerated, Table 227 initializing CXL links), “access, via the host links, registers at each device to gather information on a device's capability to route a memory request received” (section 8.1.1 configuration space registers DVSEC with capabilities. Section 8.1.3.1 DVSEC CXL capability).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine CXL Spec with Duncan so that Duncan’s address mapping is built “based on the gathered information” (CXL Spec’s capabilities) and so that Duncan’s “separate forwarding tables to indicate a device's capability.”
As stated by Applicant at [0042] of Applicant’s PGPub 2025/0284647, CXL links operate according to the PCIe specification (which Duncan utilizes).
Further, CXL Spec teaches that “CXL is a dynamic multi-protocol technology designed to support accelerators and memory devices,” “A key benefit of CXL is that it provides a low-latency, high-bandwidth path for an accelerator to access the system and for the system to access the memory attached to the CXL device,” and “CXL protocol is compatible with PCIe” (section 1.4.1).
It would have been obvious to one of ordinary skill in the art to utilize CXL links in place of PCIe links in the system of Duncan.
Duncan and CXL Spec are analogous art because they are from the same field of endeavor, which is remote memory access methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Duncan and CXL Spec before him or her, to modify the teachings of Duncan to include the teachings of CXL Spec so that the links comprise Compute Express Link (CXL) links, devices are initialized, and capability registers are read by the host and used to build an address mapping and forwarding tables.
The motivation for doing so would have been to provide a means for a low-latency, high-bandwidth path for an accelerator to access the system and for the system to access the memory attached to the CXL device (as stated by CXL Spec at 1.4.1). Further, the reading of capabilities (as described by CXL Spec) provides a means for the system to understand and properly utilize connected devices.
Therefore, it would have been obvious to combine CXL Spec with Duncan to obtain the invention as specified in the instant claim.
As per claim 41, Duncan discloses “the separate forwarding tables to be maintained at each device” ([0047] local TLB and second TLB within a destination node, TLB includes a field to indicate whether a virtual address maps to a local memory device or to a remote memory device).
CXL Spec discloses “respective registers at each device” (section 8.0 control and status registers, section 8.2 upstream and downstream port registers, section 8.2.5 CXL registers, section 8.2.6 CXL arbitration control register, Figure 139 mailbox registers).
Neither Duncan nor CXL Spec appears to explicitly disclose “respective registers at each device comprises the separate forwarding tables maintained in respective registers at each device.”
However, it is understood that the tables of Duncan are stored in some form of memory at the device. Also, as seen in CXL Spec, the devices have many registers.
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine CXL Spec with Duncan so that respective registers at each device comprises the separate forwarding tables maintained in respective registers at each device.
The motivation for doing so would have been to provide for a fast memory (registers) for storing the tables.
Note, claim 42 recites the corresponding limitations of claims 32 and 33. Therefore, the rejections of claims 32 and 33 applies to claim 42.
Note, claim 47 recites the corresponding limitations of claims 32 and 33. Therefore, the rejections of claims 32 and 33 applies to claim 47.
Claims 45 and 46 are rejected under 35 U.S.C. 103 as being unpatentable over Duncan.
As per claim 45, Duncan discloses “the instructions to cause the system to split the memory address into multiple portions” (Fig. 1A FLA ranges 102 and nodes 106. [0047] [0047] local TLB and second TLB within a destination node, TLB includes a field to indicate whether a virtual address maps to a local memory device or to a remote memory device) and “a third host link” and “a third device from among the plurality of devices” (Fig. 5B).
Duncan does not appear to explicitly disclose “the instructions to cause the system to split the memory address into multiple portions that include a third portion, wherein the system is to: send, in a third memory request via a third host link, the third portion of the memory address to a third device from among the plurality of devices, the third memory request to be forwarded to the first device via a second HSIL to access the third portion of the memory address of the memory at the first device.”
However, as above in regards to claim 44, Duncan teaches “the second memory request to be forwarded to the first device via a first high speed internal-connect link (HSIL) to access the second portion of the memory address of the memory at the first device” (Fig. 5B NVLink 310. [0042] source node configures one or more page table entries within a local TLB to map a virtual address space for the source node to the FLA space. [0043] “virtual address space that targets data residing in the one or more local system physical memory pages” and “the source node composes a remote access request that includes the FLA. In an embodiment, the FLA is within a specific FLA range 102, which is mapped to the destination node (i.e., a specific processing node 106).” [0055] “page table entries (PTEs) for the GPU MMUs 141 each include a field that indicates whether a corresponding virtual address range maps to local system physical memory or to an FLA (remote system physical memory)”).
Since Duncan teaches four devices, all connected via interconnect 302 to host and all connected via NVLink 310 (Fig. 5B), it would have been obvious to duplicate the teachings of Duncan to a third device so that “the instructions to cause the system to split the memory address into multiple portions that include a third portion, wherein the system is to: send, in a third memory request via a third host link, the third portion of the memory address to a third device from among the plurality of devices, the third memory request to be forwarded to the first device via a second HSIL to access the third portion of the memory address of the memory at the first device.”
Further, as learned from In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), it has been found that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In this case, the third device operates corresponding the previously claimed second device. No new/unexpected results are found.
As per claim 46, Duncan discloses “the instructions to cause the system to: receive, via the first host link, a first response from the first device for the first memory request, the first response to indicate a status of the access to the first portion of the memory address of the memory at the first device” (Fig. 5B each PPU has an interconnect 302 connecting to CPU 530. [0052] memory access request may comprise a read request, a write request, etc. [0079] results can be transmitted to another PPU or CPU. Fig. 5B and [0116] CPU access to each PPU’s memory, data read from the memories to be stored in the cache hierarchy of the CPU); “receive, via the second host link, a second response from the second device for the second memory request, the second response to indicate a status of the access to the second portion of the memory address of the memory at the first device” (Fig. 5B each PPU has an interconnect 302 connecting to CPU 530. [0052] memory access request may comprise a read request, a write request, etc. [0079] results can be transmitted to another PPU or CPU. Fig. 5B and [0116] CPU access to each PPU’s memory, data read from the memories to be stored in the cache hierarchy of the CPU); “and receive, via the third host link, a third response from the third device for the third memory request, the third response to indicate a status of the access to the third portion of the memory address of the memory at the first device” (Fig. 5B each PPU has an interconnect 302 connecting to CPU 530. [0052] memory access request may comprise a read request, a write request, etc. [0079] results can be transmitted to another PPU or CPU. Fig. 5B and [0116] CPU access to each PPU’s memory, data read from the memories to be stored in the cache hierarchy of the CPU).
Allowable Subject Matter
Claim 43 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application 20210133123 and Patent 11822491 teach fabric attached memory, routing tables, and NV Links.
U.S. Patent Applications 20210311900, 20210373951, 20220035701, 20220214912, 20240028526, 20250070906 and Patents 11182309, 12105952, 12197351 teach disaggregated/remote memory and CXL links
U.S. Patent Applications 20220374354, 20230236995, 20250199982, 20250202839, 20250202840, 20250202841, 20250284584, 20260064605 and Patents 12373373, 12407630, 12425358, 12500855 are pertinent art with fabric communications and/or CXL systems. However, these are all not prior to Applicant’s effective filing data and/or are also to Intel.
U.S. Patent 10769076 is the granted patent to Duncan.
WIPO Publication WO 2025171134 A1 teaches a memory fabric using CXL links and a mesh memory pooling/sharing network.
Tekin et al., ‘State-of-the-Art and Trends for Computing and Interconnect Network Solutions for HPC and AI’ teaches intra-node connectivity for CPUs, GPUs, network adapters, storage. Typically PCIe to connect storage, network adapters, and GPUs while providing high bandwidth link to connect all accelerators (NVLink).
Lutz et al., 'Pump Up the Volume: Processing Large Data on GPUs with Fast Interconnects' teaches NVLink uses address translation services to directly access any CPU memory during execution, "fast interconnects integrate the GPU into a system-wide address space, which enables us to map physical CPU pages next to GPU pages in the address space."
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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