Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 11, 12, 16-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by ISHIZUKA ET AL. (CN 1703731 A, English Equivalent translation).
Regarding claims 1, 18, 19, Ishizuka et al., figs. 3-9, discloses a driving circuit (fig. 3), wherein the driving circuit is configured to drive a light-emitting unit to emit light, and the driving circuit comprises: a voltage regulation circuit, configured to regulate a driving voltage of the light-emitting unit according to a voltage regulation signal (abstract); and a processing chip, configured to provide the voltage regulation signal to the voltage regulation circuit to reduce a difference between a reference current and a driving current of the light-emitting unit under a turned-on state (FIG. 13, firstly, the drive control circuit 4 detects reference current value IREF stored in the reference current value register 9B is less than the predetermined upper limit current value IMAX (step S31). the upper limit current value IMAX is the range of light-emission drive current to the EL element 15 light limit, the range makes the smallest brightness does not exceed a predetermined power consumption value while ensuring requirement. the new specified voltage value in the step S31, if the verification reference current value IREF is not smaller than the upper limit current value IMAX, the drive control circuit 4 before the drive voltage designating signal VD specified voltage value minus the predetermined voltage value α obtained as a result of drive voltage designating signal VD, and then converts the voltage value to the variable driving voltage generating circuit 1 (step S32), FIG. 17, the controller 22 makes the display panel 21 in all pixel portions PL1 on it, 1 to PLn, m light emitting driving state (step S41). Specifically, the controller 22 stops generating the scanning control signal and a data control signal. Then, the controller 22 sets the output voltage of the D/A converter 37 is 0V, so the offset current value is equal to zero (step S42). when the output voltage of the D/A converter 37 is 0V, the output of the offset current from the current generating circuit 38 is thereby turned off. Furthermore, the controller 22 is provided with a current measuring circuit 31 of the switch in the off position (step S43) (FIG. 4, the current detection circuit 2 is connected to the drive voltage generating circuit 1 and a display panel 10 of the anode power line 16 between resistor R1 and measuring switch SW and an A/D converter AD. When the drive control circuit 4 provides a current detection enable signal CE is logic level 1, a measuring switch SW remains disconnected, when the provided current detection enable signal CE is logic level 0 when the switch SW is turned on, so the two ends of the resistance R1 short-circuited).
Regarding claim 2, Ishizuka et al., figs. 3-9, discloses the driving circuit according to claim 1, wherein the driving circuit is configured to drive a plurality of light-emitting units to emit light, and the processing chip is further configured to output serial data for controlling the plurality of light-emitting units to be turned off or turned on; and the driving circuit further comprises: a serial-to-parallel chip, comprising an input end and a plurality of output ends, wherein the input end of the serial-to-parallel chip is configured to receive the serial data, and the serial-to-parallel chip is configured to convert the serial data into parallel data and output the parallel data through the plurality of output ends of the serial-to-parallel chip; wherein, an output end of the serial-to-parallel chip and the light-emitting unit are correspondingly provided, and the parallel data output at the output end of the serial-to-parallel chip is used for controlling a corresponding light-emitting unit to be turned off or turned on (FIG. 15, a plurality of scan lines X1 to Xn and a plurality of power lines Z1 to Zn are arranged in parallel. a plurality of data lines Y1 to Ym and a plurality of scanning lines X1 to Xn and a plurality of power lines Z1 arranged to Zn. Specifically, the controller 22 stops generating the scanning control signal and a data control signal. Then, the controller 22 sets the output voltage of the D/A converter 37 is 0V, so the offset current value is equal to zero (step S42). when the output voltage of the D/A converter 37 is 0V, the output of the offset current from the current generating circuit 38 is thereby turned off).
Regarding claim 5, Ishizuka et al., figs. 3-9, discloses the driving circuit according to claim 1, wherein the driving circuit further comprises: a first resistor, wherein the first resistor and the light-emitting unit are provided in series; wherein the processing chip is configured to provide the voltage regulation signal according to a voltage difference between two ends of the first resistor (driving device is used for according to the input image signal to drive the display panel, comprising: applying a drive voltage to the series circuit of each of the plurality of pixel portions of the driving voltage generator, and measuring from the driving voltage generator is added to the current value of the series circuit of each of the plurality of pixel portions of the current measuring element).
Regarding claims 11, 20, Ishizuka et al., figs. 3-9, discloses the driving circuit according to claim 1, wherein the driving circuit further comprises: a plurality of first resistors, wherein a first resistor and the light-emitting unit are correspondingly provided, and the first resistor and the light-emitting unit corresponding to the first resistor are provided in series; wherein the processing chip is configured to provide the voltage regulation signal according to voltage differences between two ends of the plurality of first resistors (see FIG. 16, a current measuring circuit 31 inserted between the power supply circuit 27 and the current summing circuit 29. a current measuring circuit 31 has a resistor R and a switch SW connected in parallel, so that the switch SW is closed, current from the power supply circuit 27 through the switch SW is supplied to the power supply circuit, when the switch SW is off, current from the power supply circuit 27 through the resistor R supplied to the power supply circuit. the switching state of the switch SW is controlled by the controller 22. a current measuring circuit 31 outputs the voltage corresponding to the current value flowing through the resistor R, i.e., the voltage at two ends of the resistor R).
Regarding claim 12, Ishizuka et al., figs. 3-9, discloses the 12. The driving circuit according to claim 11, wherein the processing chip is configured to provide the voltage regulation signal according to one of following: an average value of the voltage differences between two ends of the plurality of first resistors; and median value of the voltage differences between two ends of the plurality of first resistors (the average value of the measured current value is a mode of keeping in the range defined by the lower limit current value IMIN and the upper limit current value IMAX of the adjusted driving voltage Vc. In this case, the drive control circuit 4 is stored in the light-emission drive current value memory 8 each pixel in determining a measured average value of the current value, and using the value as the reference current value IREF in FIG. 13 step S31 operation of the S35).
Regarding claim 16, Ishizuka et al., figs. 3-9, discloses the driving circuit according to claim 1, wherein the driving circuit further comprises: a temperature sensor, configured to detect a temperature of the light-emitting unit; wherein the processing chip is configured to provide the voltage regulation signal according to the temperature of the light-emitting unit (Therefore, even as, for example, variation of the manufacturing process, the change of the ambient temperature or because of accumulation of the result of emission life occurrence of change of the internal resistance value of the EL element 15, display board 10 of the whole screen luminance level can be maintained within a desired brightness range. Furthermore, it can drive voltage Vc is set upper limit, in order to protect the display panel. has the above characteristics, even if the temperature changes or the luminous period of accumulation caused by the fluctuation of the internal resistance of the EL element, it can keep the display board 21 of the luminance level of the whole display area).
Regarding claim 17, Ishizuka et al., figs. 3-9, discloses the driving circuit according to claim 1, wherein the light-emitting unit is an organic light emitting diode (OLED)light-emitting unit (FIG. 1 briefly shows the active matrix drive type EL display device of the present invention; FIG. 2 shows a diagram of the internal structure of the EL unit E comprises pixels; FIG. 3 a structure diagram of an active matrix drive type EL display device of the present invention, FIG. 4 shows a current detection circuit 2 the internal structure diagram illustrating the embodiment of FIG. 5 shows the embodiment in the form of a light emitting drive, wherein the drive comprises one frame period is divided into three subframe SF1 to SF3; FIG. 6 is introduced by the drive control circuit 4 performs light emission driving current measuring program flowchart of FIG. 7 is introduced by the drive control circuit 4).
Allowable Subject Matter
Claims 3, 4, 6-10, 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the references cited in record disclose or suggest the driving circuit according to claim 5, wherein the processing chip is configured to provide the voltage regulation signal by using a preset algorithm; and the preset algorithm comprises: obtaining a total voltage required across two sides of the light-emitting unit and the first resistor according to a formula of Vd=Vc*R1*I/V1 under the turned-on state of the light-emitting unit; wherein R1 is a resistance value of the first resistor, V1 is a voltage difference between two ends of the first resistor, Vc is a total voltage across two sides of the light-emitting unit and the first resistor before the driving voltage of the light-emitting unit is regulated, Vd is the total voltage required across two sides of the light-emitting unit and the first resistor, and I is the reference current; and the processing chip is configured to obtain a corresponding voltage regulation signal according to the total voltage required across two sides of the light-emitting unit and the first resistor; and/or the driving circuit according to claim 5, wherein the driving circuit further comprises: a differential amplification circuit, wherein two input ends of the differential amplification circuit are respectively connected to the two ends of the first resistor, and an output end of the differential amplification circuit is connected to the processing chip; wherein the processing chip is configured to provide the voltage regulation signal according to a voltage of the output end of the differential amplification circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VAN N CHOW/Primary Examiner, Art Unit 2627