DETAILED ACTION
Summary and Status of Claims
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Application No. 18/860,340 filed 10/28/2024.
Claims 1-16 are pending.
Claims 1-16 are rejected under 35 U.S.C. 112(b).
Claims 1-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Akizawa et al. (US Patent Pub 5,452,451) in view of Inoue (US Patent Pub 2015/0154317).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Akizawa et al. (US Patent Pub 5,452,451) in view of Inoue (US Patent Pub 2015/0154317), further in view of Sugiyama et al. (US Patent Pub 2014/0358965).
Priority
This application is a 371 national stage of PCT/JP2023/016310 filed 4/25/2023. The application also claims foreign priority to Japanese Application JP2022-072188 filed 4/26/2022 and Japanese Application JP2022-147080 filed 9/15/2022. All certified foreign priority documents have been received and acknowledged.
Information Disclosure Statement
The information disclosure statement filed 4/23/2025 has been fully considered, initialed, and signed by the Examiner. A copy is attached to this Office action.
Drawings
The drawings are objected to because many of the drawings contain letters, numbers, and reference characters that are extremely small and do not appear to be at least .32cm (1/8 inch) in height. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it fails to comply with the requirements discussed above. It is not a single paragraph and the second paragraph is written in the form of a claim. Correction is required. See MPEP § 608.01(b).
The disclosure is objected to because of the minor informalities. SOME examples are listed below. However, Applicant’s cooperation is requested to review and correct any remaining informalities in the specification:
At para. 0018, “ASKII” should be “ASCII”.
At para. 0554, “Whereas” should be “whereas”.
Appropriate correction is required.
The disclosure is objected to because it contains an embedded hyperlink and/or other form of browser-executable code on page 59. Applicant is required to delete the embedded hyperlink and/or other form of browser-executable code; references to websites should be limited to the top-level domain name without any prefix such as http:// or other browser-executable code. See MPEP § 608.01.
The use of the term, which is a trade name or a mark used in commerce, has been noted in this application at para. 0501. The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 3 is objected to because of the following informalities:
In Claim 3, “the character string detection circuit” should be “the character string detection circuits” for consistency with base claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites “the consecutive character string” in the last limitation. It is unclear which “consecutive character string” is being referenced and potentially lacks antecedent basis. Clarification is required.
Claim 2 recites “N logic operation (logical product (AND), logical sum (OR), and/or logical negation (NOT)) circuits …” in the third limitation. The use of parentheses renders the limitation indefinite because it is unclear whether the elements within the parentheses are all required or if they are simply listed as examples of an “N logic operation”. In the latter case, the limitation renders the claim indefinite because it is unclear whether the limitation(s) are part of the claimed invention. See MPEP § 2173.05(d).
Claim 3 recites “FG shift circuit” and later “FG (flag)”. It is unclear what “FG” stands for. If “FG” is two letter representation of “flag”, then the proper recitation would be “flag (FG) shift circuit” after which “FG” can be utilized and is understood as a representation of “flag”. However, as recited, it is unclear what “FG” means and if the “(flag)” is a type of “FG” or an example. Clarification is required.
Claim 3 also recites “the character storage position” in the second limitation. It is unclear which “character storage position” of the “storage positions” detected by the “character detection circuits” is being referenced. Clarification is required.
Claim 3 also recites “a position (address)” in the second limitation. It is unclear what is intended by the use of the parentheses in this limitation. Clarification is required.
Claim 3 also recites “the character string” in the third limitation. It is unclear whether this refers to any “character string” stored on the character storage elements or a result character string. Clarification is required.
The third limitation of claim 3 is also unclear as written. For example, it is unclear what the portion “which the character string matching the character string specified by the search keyword” is intended to mean and how it relates to the other parts of the limitation. For the prior art rejections below, the limitation is interpreted as best understood by the Examiner.
Claim 4 recites “FG”. It is unclear what this acronym stands for and should be expanded. Based on the limitation “FG” seems to represent “flag” and is interpreted as such.
Claim 4 also recites “the same” in the third limitation. It is unclear what “the same” refers to as it could refer to performing the “tournament operations”, the ‘shifting the FGs”, or the “N-parallel logic operations”. Clarification is required.
Claim 5 recites “the number of shifts” in the second limitation. There is a lack of antecedent basis for this limitation in the claim.
Claim 5 recites “the FG shift circuits” in the second limitation. First, it is unclear what “FG” means or represents. Clarification is required. Second, there is lack of antecedent basis for this limitation in the claim.
Claim 5 also recites “the number of tournament operations” and “the FG tournament operational circuits” in the second limitation. There is lack of antecedent basis for these limitations in the claim.
Claim 6 recites “the FG tournament circuits”. There is lack of antecedent basis for this limitation in the claim.
Claim 6 also recites “masking (ignoring)”. Applicant’s use of parentheses makes the limitation indefinite as it is unclear what is intended as part of Applicant’s claimed invention. Clarification is required.
Claim 7 recites “the FG tournament circuit”. There is lack of antecedent basis for this limitation in the claim.
Claim 8 recites “logical sum (OR) operation” on line 2. Applicant’s use of parentheses makes the limitation indefinite because it is unclear what is intended as part of Applicant’s claimed invention. Clarification is required.
Claim 8 also recites “the N-parallel (full parallel) detection results output …” in lines 2-3. There is lack of antecedent basis for this limitation in the claim. While there are “result output circuits” in base claim 1, these circuits merely output a “position.” Also, Applicant’s use of parentheses makes it unclear whether the items in the parentheses are required. Clarification is required.
Claim 9 recites “text data” on line 2. It is unclear whether “text data” is new text data or another instance of text data, or refers to the “search target text data” recited in claim 1. Clarification is required.
Claim 9 also recites “the N-byte character text data” in line 4. It is unclear if this refers to the stored “search target text data” or to any text data stored in the “character storage elements”. Clarification is required.
Claim 9 further recites “the full-text search operations” in lines 4-5. It is unclear what is encompassed by the limitation and it is not defined by the based claim. Therefore, there is a lack of antecedent basis for this limitation in the claim.
Claim 9 further recites “N-parallel (full parallel)”. Applicant’s use of parentheses makes it unclear whether the items in the parentheses are required. Clarification is required.
Claim 10 recites similar limitations as claim 9 and is rejected for the same reasons.
Claims 11 and 12 recite the acronyms “ASICs”, “FPGAs”, and “CPU” which should be expanded to clarify their intended meanings.
Claim 13 recites “such as UTF-8”, which renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Claim 14 recites “the full-text search operations” in line 4. It is unclear what is encompassed by the limitation and it is not defined by the based claim. Therefore, there is a lack of antecedent basis for this limitation in the claim.
Claim 15 recites “the latest information”. There is lack of antecedent basis for this limitation in the claim. It is unclear what the limitation encompasses.
Claim 16 recites “the latest information”. There is lack of antecedent basis for this limitation in the claim. It is unclear what the limitation encompasses.
The prior art rejections below are made as best understood in light of the rejections set forth under 112(b) above.
Note on Prior Art Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Akizawa et al. (US Patent Pub 5,452,451) (Akizawa) in view of Inoue (US Patent Pub 2015/0154317).
In regards to claim 1, Akizawa discloses a full-text search processor consisting of semiconductor devices intended for full-text keyword searches, the full-text search processor comprising:
character storage elements for receiving search target text data to be searched through, and assigning and temporarily storing therein, a coded character string included in the text data to a first address to an Nth address byte by byte (Akizawa at col. 11, lines 34-61; col. 14, lines 60-66)1;
character detection circuits for detecting storage positions, on the character storage elements, of all of coded characters included in a search keyword by sequentially receiving one or more coded characters included in the search keyword byte by byte as comparison data, comparing each of the comparison data with the coded character string stored on the character storage elements in N-parallel, and repeating it for all of the coded characters included in the search keyword (Akizawa at col. 11, lines 34-67; col. 12, lines 1-4; col. 13, lines 40-63)2
character string detection circuits for detecting positions on the character storage elements where all of the coded characters included in the search keyword exist consecutively in the same order as in the search keyword (Akizawa at col. 6, lines 41-51; col. 13, 40-63)3; and
Akizawa does not expressly disclose result output circuits for receiving search results of the character string detection circuits and outputting a position of the beginning or a position of the end of the consecutive character string. It is noted Akizawa does disclose an output buffer that holds the result of the search to be output therefrom. Akizawa at col. 11, lines 59-60.
Inoue discloses a memory with a set operation function for processing information, including pattern matching (i.e., text searching). Inoue at paras. 0021-22. The result of the pattern matching is output of an address (i.e., position) of the matched information (i.e., result output circuits … outputting a position … of the consecutive character string). Inoue at paras. 0147-150.
Akizawa and Inoue are analogous art because they are directed to the same field of endeavor of string/text searching.
At the time before the effective filing date of the instant application, it would have been obvious to one of ordinary skill in the art to modify Akizawa by adding the features of result output circuits for receiving search results of the character string detection circuits and outputting a position of the beginning or a position of the end of the consecutive character string, as disclosed by Inoue.
The motivation for doing so would have been to determine an absolute address, in memory, of the information being detected. Inoue at para. 0180.
In regards to claim 2, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the character detection circuits comprise
N sets of eight 1-bit match or mismatch operational circuits, connected to each address of the character storage elements, for comparing a 1-byte/8-bit code of the text data stored at each address and a 1-byte/8-bit code constituting the comparison data, and detecting a bit-by-bit match or mismatch (Akizawa at col. 15, lines 56-68; col. 16, lines 1-7)4; and
N logic operation (logical product (AND), logical sum (OR), and/or logical negation (NOT)) circuits for receiving 8 bits of result output from each set of the 1-bitmatch or mismatch operational circuits, and detecting a match or mismatch between a character code of the coded characters of the text data stored at each address and a character code of coded characters constituting the comparison data. Inoue at para. 0145.5
In regards to claim 3, Akizawa in view of Inoue discloses the full-text search processor of Claim 1,
wherein the character string detection circuit is composed of two circuits: an FG shift circuit and an FG tournament circuit for determining validity of a FG (flag) at the character storage position detected by the character detection circuit and a FG (flag) sequence at the detected character storage positions (Inoue at paras. 0166, 0184, 284-5), and
the FG shift circuit and the FG tournament circuit are circuits for detecting in N- parallel, a position (address) of the beginning or a position (address) of the end of the character codes of the character string on the character storage elements, which the character string matching the character string specified by the search keyword, by referring to a sequence of the character codes of coded characters included in the search keyword and repeatedly determining the validity of a sequence of adjacent character codes in the character codes of the character string on the character storage elements, assigned and stored at the first address to the Nth address. Inoue at paras. 0166, 0184, 284-5. Akizawa at col. 13, lines 40-64.6
In regards to claim 4, Akizawa in view of Inoue discloses the full-text search processor of claim 1, wherein:
the character string detection circuits comprise
N of FG shift circuits for storing operation results of the character detection circuits as flags as well as shifting the stored FGs in N-parallel (Inoue at paras. 0166, 0184)7; and
N of FG tournament circuits for performing tournament operations on the FGs by shifting the FGs, stored by the FG shift circuits, in N-parallel while performing N-parallel logic operations on the FGs with the pre-shifting FGs, and repeating the same for all of the coded characters included in the search keyword. Inoue at paras. 0284-5.8
In regards to claim 5, Akizawa in view of Inoue discloses the full-text search processor of Claim 1,
wherein when the search keyword is constituted with n-byte coded characters (Akizawa at col. 11, lines 34-41; col. 14, lines 67-68; col. 15, lines 1-6, 56-63)9,
the number of shifts of the FG shift circuits and its associated the number of tournament operations by the FG tournament operational circuits are n x 2-1times, respectively. Akizawa at col. 13, lines 40-64.10
In regards to claim 6, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the FG tournament circuits comprise a function for enabling masking (ignoring) of operations and enable a full-text search when a wildcard is used in the search keyword. Inoue at paras. 0191, 0523.11
In regards to claim 7, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the FG tournament circuit is incorporated with two pairs of registers and enable a full-text search when the search keyword includes a character gap. Akizawa at Fig. 42; col. 30, lines 47-61.12
In regards to claim 8, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the full-text search processor performs a logical sum (OR) operation on the N- parallel (full parallel) detection results output by the result output circuits, and outputs presence or absence of full-text search operations. Akizawa at Fig. 12.13 Inoue at para. 0501.14
In regards to claim 9, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the full-text search processor transfers text data, which is in memories or storage external to the full-text search processor, to character storage elements, which are for temporarily storing the N-byte character text data, as batch data; and repeats the full-text search operations in N-parallel (full parallel). Akizawa at col. 11, lines 34-41; col. 12, lines 1-4. Inoue at Fig. 21; para. 0154.15
In regards to claim 10, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the full-text search processor transfers text data, which is in memories or storage inside the full-text search processor, to character storage elements, which are for temporarily storing the N-byte character text data, as batch data; and repeats the full-text search operations in N-parallel (full parallel). Akizawa at col. 11, lines 34-41; col. 12, lines 1-4. Inoue at para. 0154.16
In regards to claim 11, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the full-text search processor is implemented in ASICs and FPGAs. Inoue at paras. 0264-265, 0333.17
In regards to claim 12, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein the full-text search processor has a CPU incorporated therein. Akizawa at col. 22, lines 15-17.
In regards to claim 14, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein when predetermined character codes are included in a character string of an externally given search keyword, the full-text search processor performs or does not perform the full-text search operations. Akizawa at col. 11, lines 35-41.18
In regards to claim 15, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein by matching a part of a sentence being composed with the full-text search processor, which has therein accumulated text data that incorporates a large amount of the latest information, if there is no matching text, the full-text search processor determines that there is no precedent. Inoue at paras. 0168, 0650.19
In regards to claim 16, Akizawa in view of Inoue discloses the full-text search processor of Claim 1, wherein when selecting an optimal recognition result among a plurality of recognition candidates of speech recognition, by matching with the full-text search processor, which has therein accumulated text data that incorporates a large amount of the latest information, and selecting terms with the most matching text, the full-text search processor improves accuracy of speech recognition. Inoue at paras. 0168, 0596.20
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Akizawa et al. (US Patent Pub 5,452,451) (Akizawa) in view of Inoue (US Patent Pub 2015/0154317), further in view of Sugiyama et al. (US Patent Pub 2014/0358965) (Sugiyama).
In regards to claim 13, Akizawa in view of Inoue discloses a method for using the full-text search processor of Claim 1, but does not expressly disclose comprising the step of: applying a world standard character code such as UTF-8 to thereby enable universal full-text search for all characters worldwide.
Sugiyama discloses a method of searching a character string by comparing units of bit sequences. The method includes support for multibyte character encodings, such as UTF-8. Sugiyama at abstract; para. 0024.
Akizawa, Inoue, and Sugiyama are analogous art because they are directed to the same field of endeavor of text searching.
At the time before the effective filing date of the instant application, it would have been obvious to one of ordinary skill in the art to modify Akizawa in view of Inoue by adding the features of applying a world standard character code such as UTF-8 to thereby enable universal full-text search for all characters worldwide, as disclosed by Sugiyama.
The motivation for doing so would have been to support more languages, since multibyte character encodings support all languages while ascii is only single byte and cannot support all languages. Sugiyama at para. 0024.
Additional Prior Art
Additional relevant prior art are listed on the attached PTO-892 form. Some examples are:
Tada et al. (US Patent 5,745,745) discloses a text search method for structured documents.
Ichiriu et al. (US Patent 7,529,746) discloses a search circuit with individually selectable search engines.
Ninan et al. (US Patent 7,539,031) discloses a system and method for inexact pattern searching using bitmaps.
Takahashi (US Patent 4,958,377) discloses a system and method for character string identification device with a memory using selectively accessible memory areas.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Michael Le whose telephone number is 571-272-7970 and fax number is 571-273-7970. The examiner can normally be reached Mon-Fri 9:30 AM – 6 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tony Mahmoudi can be reached on 571-272-4078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL LE/Examiner, Art Unit 2163
/TONY MAHMOUDI/Supervisory Patent Examiner, Art Unit 2163
1 Information to be searched (i.e., target text data) is stored in a CAM (i.e., storage elements), byte by byte.
2 The input character code is received to perform the comparison with the text data to be searched, in parallel, until a sequence of characters is detected.
3 A sequence of characters (i.e., coded characters … exist consecutively in the same order) are detected in the text to be searched, where character position information is determined.
4 Each character is compared and collated bit by bit through each character byte (i.e., character code) with the input data.
5 The system provides memory with the functionality to perform logical operations when performing comparison.
6 Inoue discloses shift registers and tournament operations for performing the search to return an address (i.e., position) as a result of finding a match. Akizawa discloses ensuring the sequence of characters match as it goes through each character for comparison (i.e., determining the validity of the sequence …).
7 Shift registers for managing flags in the CAM.
8 Circuits also include performing tournament operations on flags while doing the comparison for string searching/matching.
9 The input data is compared bit by bit by respective byte (i.e., search keyword is constituted of n-byte code characters).
10 The number of steps depends on how many consecutive characters are matched. This ensure the validity of the sequence.
11 The combined system enables masking and full text searching using wild cards.
12 The combined system provides corresponding registers (i.e., two pairs of registers) for full text searching. Here a character gap is interpreted as a space, which would have its own character code.
13 As shown in Fig. 12, portion 212-16, there are a series of logical OR gates that are performed in parallel based on detection results.
14 Inoue also discloses use of logical OR of the matched address (i.e., based on the detection results).
15 The combination discloses storing text data in a 1 byte CAM (i.e., storing N-byte character text data in storage elements), where the search operations can be performed in parallel. Here the memory is “inside the processor” as opposed to an external database storage SSD (external the processor).
16 The combination discloses storing text data in a 1 byte CAM (i.e., storing N-byte character text data in storage elements), where the search operations can be performed in parallel.
17 The system is implemented using FPGA and ASIC.
18 The limitation is interpreted either being performed when an input string (i.e., search keyword with character codes) is received. It is interpreted as being “externally given” because it is not derived from the storage because it is “input”.
19 If no match is found, no addresses are output (i.e., determines there is no precedent). The system can perform full text searching and text to be searched is interpreted as the “latest information”.
20 The system supports full text searching of synthesized speech (i.e., speech recognition).