DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5, 8, 11, 12, 15, 18, 19, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shigeta et al (US 2018/0293929; hereinafter Shigeta).
• Regarding claims 1, 8, and 15, Shigeta discloses a display, pixel drive circuit, and method (figures 11 and 12) comprising:
an array of micro-LEDs (µLEDs) (elements 100 in figure 11 and element 130 in figures 1 and 2 and ¶s 50-53); and
a pixel drive circuit configured to drive each uLED of the array (elements 110, 120, and 140 in figures 1 and 2 ¶s 54-57),
each pixel drive circuit comprising:
a drive transistor including a gate terminal configured to control a gate voltage of the drive transistor based on a demura compensation voltage signal to control a current supplied to the µLED to adjust an amount of light emitted by the µLED (element 125-1 in figure 2A and ¶s 54-57 and 241; where the claimed “demura compensation” is seen to be equivalent to the disclosed corrections made to Va and Vw “to heighten the luminance uniformity” and where ¶s 87 and 88 disclose where Va is applied to the gate of element 125-1 in figure 4A via element 112),
wherein a value of the demura compensation is based on at least one of a temperature of the pixel drive circuit and a desired brightness of the µLED (¶ 241, as previously explained).
• Regarding claims 4, 5, 11, 12, 18, 19, and 21-23, Shigeta discloses everything claimed, as applied to claims 1, 8, and 15. Additionally, Shigeta discloses where:
Claims 4, 11, & 18: the pixel drive circuit further comprises a capacitor configured to store a value of the demura compensation (element 111 in figure 10B in view of ¶s 181 and 241).
Claims 5, 12, & 19: the pixel drive circuit further comprises a transistor configured to store a value of the demura compensation (element 112 in figure 10B in view of ¶s 181 and 241).
Claims 21-23: the pixel drive circuit comprises:
the µLED (element 130 in figures 1 and 2 and ¶s 50-53),
the µLED includes an electrode electrically connected to the drive transistor to allow current to flow from the drive transistor through the µLED (note the relationship between elements 125 and 130 in figure 2 and ¶ 54).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 13, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shigeta, in view of Genoe (US 2015/0317951).
• Regarding claims 6, 7, 13, 14, and 20, Shigeta discloses everything claimed, as applied to claims 1, 8, and 15. However, Shigeta fails to disclose the additional details of the display, pixel drive circuit, and method.
In the same field of endeavor, Genoe discloses where:
Claims 6, 13, & 20: the pixel drive circuit further comprises:
a dual gate transistor configured to store a pixel value and a value of the demura compensation (elements C1, C2, and M1 in figure 7 and ¶s 71-73).
Claims 7 & 14: the value of the demura compensation is stored while the display is off (¶ 71).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Shigeta according to the teachings of Genoe, for the purpose of driving the pixels in a display at substantially the same current (¶ 67).
Response to Arguments
Applicant's arguments filed 02 October 2025 have been fully considered but they are not persuasive.
a. Regarding applicant’s argument that “[t]he compensation circuit 1000 described in Shigeta does not apply a demura compensation voltage signal that is based on at least one of a temperature of the pixel drive circuit or a desired brightness of the PLED to a gate terminal of a drive transistor” (page 6), the examiner disagrees. Figure 10A and ¶ 209 discloses where “[t]he D/A converter 1020 may apply the amplitude setup voltage Va and the pulse width setup voltage Vw of the drive current Id corresponding to the image data or the image data corrected by the corrector 1010 to the data signal line 410” and ¶ 88 discloses where “the amplitude setting circuit 110 of the pixel circuit 400 may charge the capacitor 111 with the amplitude setup voltage Va applied through a data signal line 410 while the transistor 112 is turned on in accordance with the control signal GATE(n) input to the gate terminal of the transistor 112, and may apply the voltage charged in the capacitor 111 to the gate terminal of the driving transistor 125-1”. Therefore, Shigeta teaches the invention of claims 1, 8, and 15.
Closing Remarks/Comments
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622