Prosecution Insights
Last updated: July 17, 2026
Application No. 18/861,543

DATA PROCESSING METHOD AND APPARATUS

Non-Final OA §103§112
Filed
Oct 29, 2024
Priority
Jun 17, 2022 — CN 202210689985.8 +1 more
Examiner
CHAPPELL, DANIEL C
Art Unit
2135
Tech Center
2100 — Computer Architecture & Software
Assignee
Cloud Intelligence Assets Holding (Singapore) Private Limited
OA Round
2 (Non-Final)
81%
Grant Probability
Favorable
2-3
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
489 granted / 607 resolved
+25.6% vs TC avg
Strong +47% interview lift
Without
With
+46.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
15 currently pending
Career history
618
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
75.2%
+35.2% vs TC avg
§102
5.2%
-34.8% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 607 resolved cases

Office Action

§103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This Office action is in response communications dated 4/3/2026. Claims 1, 3-6, 8-10, 12-13, 15-18, and 20-21 are amended. Claim 11 is cancelled. Claims 1-10 and 12-21 are pending. Claims 10 and 12-13 are rejected. The text of those sections of Title 35, U. S. Code not included in this action can be found in a prior Office action. Claim Rejections - 35 USC § 112 The Examiner thanks Applicant for amending the claims to cure the deficiencies under 35 U.S.C. §112(b) notes in the non-final Office action dated 1/7/2026 and therefore respectfully withdraws the rejections of claims 1-10 and 12-21 under 35 U.S.C. §112(b) made therein. Claim Rejections - 35 USC § 103 Claims 1 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over the attached machine translation of Chinese patent document CN114117111A (“MT111”) in view of the attached machine translation of Chinese patent document CN112579595A (“MT595”) and further in view of USPGPUB 2011/0191628 (“Noguchi”) and further in view of USPGPUB 2015/0293717 (“Kesavan”). As per claim 1, MT111 substantially teaches a data processing method (MT111, paragraph n0049), comprising: reading the index data written to the magnetic disk file and the allocation state written to the magnetic disk file from the magnetic disk file upon restarting an in-memory database containing the memory allocation area; mapping the index data read from the magnetic disk file to the memory allocation area according to the regional address: (MT111, paragraphs n0048-n0126, where the system of MT111 acquires image information at a local machine to be retrieved from a remote server. A feature vector (i.e., in-memory database) corresponding to the image information to be retrieved is extracted from the image information to be retrieved and stored (i.e., written) to a hard disk of a local machine. The feature vector is transmitted to a remote server for storage in one or more hard disks of the remote server. Once stored in the one or more hard disks of the remote server, the feature vector is compared to pre-stored feature vectors stored at the remote server. The Examiner notes that the system of MT111 periodically backs up the pre-stored feature vectors stored at the remote server to enable faster restart of operations if the pre-stored feature vectors stored at the remote server are lost. When a match for the feature vector is found in storage of the remote server, the remote server updates a mapping of information to be sent to the local machine. MT111 therefore substantially teaches reading the index data written to the magnetic disk file and the allocation state written to the magnetic disk file from the magnetic disk file upon restarting an in-memory database containing the memory allocation area; mapping the index data read from the magnetic disk file to the memory allocation area according to the regional address). MT111 does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, MT595 particularly teaches: determining a memory allocation area corresponding to a regional address and a memory allocator associated with the memory allocation area; obtaining index data of the memory allocation area and an allocation state of the memory allocator associated with the memory allocation area; and writing the index data of the memory allocation area and the allocation state of the memory allocator associated with the memory allocation area to a magnetic disk file: (MT595, paragraphs n004-n0068, where the system of MT595 receives a write operation that includes data to be processed by the write operation. The system of MT595 determines a free area of memory that may be used to store the data to be processed by the write operation and updates a mapping table to indicate that the free area of memory has been allocated for storage of the data to be stored. The data to be stored, along with the updated mapping table, are then stored to a hard disk. MT595 therefore particularly teaches determining a memory allocation area corresponding to a regional address and a memory allocator associated with the memory allocation area; obtaining index data of the memory allocation area and an allocation state of the memory allocator associated with the memory allocation area; and writing the index data of the memory allocation area and the allocation state of the memory allocator associated with the memory allocation area to a magnetic disk file). It would have been obvious to a person having ordinary skill in the art, having the teachings of MT595 and MT111 before them before the instant application was effectively filed, to modify the system of MT111 to include the principles of data storage of MT595. The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by ensuring that data write operations are written in multiple places within a disk in order to mitigate data loss. Neither MT111 nor MT595 appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Noguchi teaches computer program, method, and apparatus for controlling data allocation. As per claim 1, Noguchi particularly teaches: and performing an update on a state of the memory allocator according to the allocation state: (Noguchi, Abstract; FIG. 18; and paragraphs 0059 and 0198-0202, where the system of Noguchi receives a data access request to access data stored at an address on a disk drive. The Examiner notes that the data requested to be accessed may be stored to multiple locations within the disk drive in order to increase data redundancy. In the event the data access request encounters an error, a status of the data access request is updated and sent to a requesting entity (i.e., the memory allocator) for the request. Noguchi therefore particularly teaches and performing an update on a state of the memory allocator according to the allocation state). It would have been obvious to a person having ordinary skill in the art, having the teachings of Noguchi and performing an update on a state of the memory allocator according to the allocation state595, and MT111 before them before the instant application was effectively filed, to modify the combination of MT595 with MT111 to include the principles of monitoring status of data access requests of Noguchi. The modification would have been obvious because a person having ordinary skill in the art would be motivated to implement techniques for data monitoring in order to reduce the probability of data loss (Noguchi, paragraph 0059). None of MT111, MT595, or Noguchi appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Kesavan teaches modular block-allocator for data storage systems. As per claim 1, Kesavan particularly teaches: performing an update on a state of the memory allocator associated with the memory allocation area according to the allocation state read from the magnetic disk file: (Kesavan, Abstract; and paragraphs 0006-0007, where data requested from allocated disk blocks by are retrieved (i.e., read) from magnetic disk and stored in cache. When the retrieved data is modified (i.e., updated) while stored in cache, the retrieved data in the cache is updated in the cache until finally being written back to disk (i.e., the magnetic disk file). Kesavan therefore particularly teaches performing an update on a state of the memory allocator associated with the memory allocation area according to the allocation state read from the magnetic disk file). It would have been obvious to a person having ordinary skill in the art, having the teachings of Kesavan, Noguchi, MT595, and MT111 before them before the instant application was effectively filed, to modify the combination of Noguchi with the combination of MT595 with MT111 to include the principles of Kesavan of allowing modification of cached storage blocks. The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system flexibility by implementing modular block allocation techniques that scale with increasing numbers of processors allocating storage (Kesavan, paragraph 0031). As per claim 12, MT111 substantially teaches a data processing apparatus (MT111, paragraph n0049), comprising: read the index data written to the magnetic disk file and the allocation state written to the magnetic disk file from the magnetic disk file upon restarting an in-memory database containing the memory allocation area; map the index data read from the magnetic disk file to the memory allocation area according to the regional address: (MT111, paragraphs n0048-n0126, where the system of MT111 acquires image information at a local machine to be retrieved from a remote server. A feature vector (i.e., in-memory database) corresponding to the image information to be retrieved is extracted from the image information to be retrieved and stored (i.e., written) to a hard disk of a local machine. The feature vector is transmitted to a remote server for storage in one or more hard disks of the remote server. Once stored in the one or more hard disks of the remote server, the feature vector is compared to pre-stored feature vectors stored at the remote server. The Examiner notes that the system of MT111 periodically backs up the pre-stored feature vectors stored at the remote server to enable faster restart of operations if the pre-stored feature vectors stored at the remote server are lost. When a match for the feature vector is found in storage of the remote server, the remote server updates a mapping of information to be sent to the local machine. MT111 therefore substantially teaches read the index data written to the magnetic disk file and the allocation state written to the magnetic disk file from the magnetic disk file upon restarting an in-memory database containing the memory allocation area; map the index data read from the magnetic disk file to the memory allocation area according to the regional address). MT111 does not appear to explicitly teach the other limitations of claim 12 beyond those taught above; however, in an analogous art, MT595 particularly teaches: determine a memory allocation area corresponding to a regional address and a memory allocator associated with the memory allocation area; obtain index data of the memory allocation area and an allocation state of the memory allocator associated with the memory allocation area; and write the index data of the memory allocation area and the allocation state of the memory allocator associated with the memory allocation area to a magnetic disk file: (MT595, paragraphs n004-n0068, where the system of MT595 receives a write operation that includes data to be processed by the write operation. The system of MT595 determines a free area of memory that may be used to store the data to be processed by the write operation and updates a mapping table to indicate that the free area of memory has been allocated for storage of the data to be stored. The data to be stored, along with the updated mapping table, are then stored to a hard disk. MT595 therefore particularly teaches determine a memory allocation area corresponding to a regional address and a memory allocator associated with the memory allocation area; obtain index data of the memory allocation area and an allocation state of the memory allocator associated with the memory allocation area; and write the index data of the memory allocation area and the allocation state of the memory allocator associated with the memory allocation area to a magnetic disk file). It would have been obvious to a person having ordinary skill in the art, having the teachings of MT595 and MT111 before them before the instant application was effectively filed, to modify the system of MT111 to include the principles of data storage of MT595. The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by ensuring that data write operations are written in multiple places within a disk in order to mitigate data loss. Neither MT111 nor MT595 appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Noguchi teaches computer program, method, and apparatus for controlling data allocation. As per claim 12, Noguchi particularly teaches: a memory and a processor, wherein the memory is configured to store computer executable instructions, and the processor is configured to execute the computer executable instructions which, when executed by the processor, cause to the processor to: (Noguchi, Abstract, where the system of Noguchi comprises a computer to execute a data allocation control program to control allocation of data in a plurality of disk nodes. The Examiner notes that the computer of Noguchi, since it executes the data allocation control program, must comprise both a processor to execute the computer instructions of the data allocation control program and memory to store the data allocation control program. Noguchi therefore particularly teaches a memory and a processor, wherein the memory is configured to store computer executable instructions, and the processor is configured to execute the computer executable instructions which, when executed by the processor, cause to the processor to); and perform an update on a state of the memory allocator according to the allocation state: (Noguchi, Abstract; FIG. 18; and paragraphs 0059 and 0198-0202, where the system of Noguchi receives a data access request to access data stored at an address on a disk drive. The Examiner notes that the data requested to be accessed may be stored to multiple locations within the disk drive in order to increase data redundancy. In the event the data access request encounters an error, a status of the data access request is updated and sent to a requesting entity (i.e., the memory allocator) for the request. Noguchi therefore particularly teaches and perform an update on a state of the memory allocator according to the allocation state). It would have been obvious to a person having ordinary skill in the art, having the teachings of Noguchi and performing an update on a state of the memory allocator according to the allocation state595, and MT111 before them before the instant application was effectively filed, to modify the combination of MT595 with MT111 to include the principles of monitoring status of data access requests of Noguchi. The modification would have been obvious because a person having ordinary skill in the art would be motivated to implement techniques for data monitoring in order to reduce the probability of data loss (Noguchi, paragraph 0059). None of MT111, MT595, or Noguchi appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Kesavan teaches modular block-allocator for data storage systems. As per claim 12, Kesavan particularly teaches: perform an update on a state of the memory allocator associated with the memory allocation area according to the allocation state read from the magnetic disk file: (Kesavan, Abstract; and paragraphs 0006-0007, where data requested from allocated disk blocks by are retrieved (i.e., read) from magnetic disk and stored in cache. When the retrieved data is modified (i.e., updated) while stored in cache, the retrieved data in the cache is updated in the cache until finally being written back to disk (i.e., the magnetic disk file). Kesavan therefore particularly teaches perform an update on a state of the memory allocator associated with the memory allocation area according to the allocation state read from the magnetic disk file). It would have been obvious to a person having ordinary skill in the art, having the teachings of Kesavan, Noguchi, MT595, and MT111 before them before the instant application was effectively filed, to modify the combination of Noguchi with the combination of MT595 with MT111 to include the principles of Kesavan of allowing modification of cached storage blocks. The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system flexibility by implementing modular block allocation techniques that scale with increasing numbers of processors allocating storage (Kesavan, paragraph 0031). As per claim 13, MT111 substantially teaches: reading the index data written to the magnetic disk file and the allocation state written to the magnetic disk file from the magnetic disk file upon restarting an in-memory database containing the memory allocation area; mapping the index data read from the magnetic disk file to the memory allocation area according to the regional address: (MT111, paragraphs n0048-n0126, where the system of MT111 acquires image information at a local machine to be retrieved from a remote server. A feature vector (i.e., in-memory database) corresponding to the image information to be retrieved is extracted from the image information to be retrieved and stored (i.e., written) to a hard disk of a local machine. The feature vector is transmitted to a remote server for storage in one or more hard disks of the remote server. Once stored in the one or more hard disks of the remote server, the feature vector is compared to pre-stored feature vectors stored at the remote server. The Examiner notes that the system of MT111 periodically backs up the pre-stored feature vectors stored at the remote server to enable faster restart of operations if the pre-stored feature vectors stored at the remote server are lost. When a match for the feature vector is found in storage of the remote server, the remote server updates a mapping of information to be sent to the local machine. MT111 therefore substantially teaches reading the index data written to the magnetic disk file and the allocation state written to the magnetic disk file from the magnetic disk file upon restarting an in-memory database containing the memory allocation area; mapping the index data read from the magnetic disk file to the memory allocation area according to the regional address). MT111 does not appear to explicitly teach the other limitations of claim 13 beyond those taught above; however, in an analogous art, MT595 particularly teaches: determining a memory allocation area corresponding to a regional address and a memory allocator associated with the memory allocation area; obtaining index data of the memory allocation area and an allocation state of the memory allocator associated with the memory allocation area, and writing the index data of the memory allocation area and the allocation state of the memory allocator associated with the memory allocation area to a magnetic disk file: (MT595, paragraphs n004-n0068, where the system of MT595 receives a write operation that includes data to be processed by the write operation. The system of MT595 determines a free area of memory that may be used to store the data to be processed by the write operation and updates a mapping table to indicate that the free area of memory has been allocated for storage of the data to be stored. The data to be stored, along with the updated mapping table, are then stored to a hard disk. MT595 therefore particularly teaches determining a memory allocation area corresponding to a regional address and a memory allocator associated with the memory allocation area; obtaining index data of the memory allocation area and an allocation state of the memory allocator associated with the memory allocation area, and writing the index data of the memory allocation area and the allocation state of the memory allocator associated with the memory allocation area to a magnetic disk file). It would have been obvious to a person having ordinary skill in the art, having the teachings of MT595 and MT111 before them before the instant application was effectively filed, to modify the system of MT111 to include the principles of data storage of MT595. The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system reliability by ensuring that data write operations are written in multiple places within a disk in order to mitigate data loss. Neither MT111 nor MT595 appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Noguchi teaches computer program, method, and apparatus for controlling data allocation. As per claim 13, Noguchi particularly teaches: a non-transitory computer readable storage medium storing computer executable instructions which, when executed by the processor, implement the following: (Noguchi, Abstract, where the system of Noguchi comprises a computer to execute a data allocation control program to control allocation of data in a plurality of disk nodes. The Examiner notes that the computer of Noguchi, since it executes the data allocation control program, must comprise both a processor to execute the computer instructions of the data allocation control program and memory to store the data allocation control program. Noguchi therefore particularly teaches a non-transitory computer readable storage medium storing computer executable instructions which, when executed by the processor, implement the following); and performing an update on a state of the memory allocator according to the allocation state: (Noguchi, Abstract; FIG. 18; and paragraphs 0059 and 0198-0202, where the system of Noguchi receives a data access request to access data stored at an address on a disk drive. The Examiner notes that the data requested to be accessed may be stored to multiple locations within the disk drive in order to increase data redundancy. In the event the data access request encounters an error, a status of the data access request is updated and sent to a requesting entity (i.e., the memory allocator) for the request. Noguchi therefore particularly teaches and performing an update on a state of the memory allocator according to the allocation state). It would have been obvious to a person having ordinary skill in the art, having the teachings of Noguchi and performing an update on a state of the memory allocator according to the allocation state595, and MT111 before them before the instant application was effectively filed, to modify the combination of MT595 with MT111 to include the principles of monitoring status of data access requests of Noguchi. The modification would have been obvious because a person having ordinary skill in the art would be motivated to implement techniques for data monitoring in order to reduce the probability of data loss (Noguchi, paragraph 0059). None of MT111, MT595, or Noguchi appears to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Kesavan teaches modular block-allocator for data storage systems. As per claim 13, Kesavan particularly teaches: performing an update on a state of the memory allocator associated with the memory allocation area according to the allocation state read from the magnetic disk file: (Kesavan, Abstract; and paragraphs 0006-0007, where data requested from allocated disk blocks by are retrieved (i.e., read) from magnetic disk and stored in cache. When the retrieved data is modified (i.e., updated) while stored in cache, the retrieved data in the cache is updated in the cache until finally being written back to disk (i.e., the magnetic disk file). Kesavan therefore particularly teaches performing an update on a state of the memory allocator associated with the memory allocation area according to the allocation state read from the magnetic disk file). It would have been obvious to a person having ordinary skill in the art, having the teachings of Kesavan, Noguchi, MT595, and MT111 before them before the instant application was effectively filed, to modify the combination of Noguchi with the combination of MT595 with MT111 to include the principles of Kesavan of allowing modification of cached storage blocks. The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system flexibility by implementing modular block allocation techniques that scale with increasing numbers of processors allocating storage (Kesavan, paragraph 0031). Response to Arguments In the Remarks dated 4/3/2026, Applicant substantially argues: None of the prior art alone or in combination teaches or suggests the claimed combination of features of the amended claims of the instant application. Applicant’s arguments dated 4/3/2026 have been fully considered, but they are moot in view of the new grounds of rejection that were necessitated by Applicant’s amendments to the claims. The Examiner notes that the new Kesavan reference in combination with MT111, MT595, and Noguchi clearly teaches the limitations added to the claims by amendment. The Examiner further notes that the new grounds of rejection were necessitated by Applicant’s amendments to the claims. Conclusion The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure: USPGPUB 2015/0242481: teaches management of data replication in data storage systems. Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Daniel C. Chappell Primary Examiner Art Unit 2135 /Daniel C. Chappell/Primary Examiner, Art Unit 2135
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Prosecution Timeline

Oct 29, 2024
Application Filed
Jan 07, 2026
Non-Final Rejection mailed — §103, §112
Apr 03, 2026
Response Filed
May 05, 2026
Final Rejection mailed — §103, §112
Jun 26, 2026
Response after Non-Final Action

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Prosecution Projections

2-3
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+46.9%)
2y 3m (~7m remaining)
Median Time to Grant
Moderate
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