DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-13 are pending. Claims 3-10 and 12-13 are rejected. Claims 1-2 and 11 are allowed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshii et el. (JP 2011066473 A), (hereinafter Yoshii)
Regarding claim 3, Yoshii teaches, an electronic circuit comprising a functional circuit having a predetermined function (Yoshii: ‘the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "functional circuit" [0034]), and a test circuit that tests the functional circuit for debugging of the functional circuit (Yoshii: ‘performs test operation in the test operation mode’ [0034]), the electronic circuit comprising:
a second input circuit configured to decode a predetermined command signal and output a decoded command signal to the functional circuit (Yoshii: ‘the dual-purpose external terminals T1, T2, T3 are used in the normal operation mode and are connected to the internal circuitry. Therefore, the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "second input circuit'' and the "functional circuit. Because the input to the dual-purpose external terminals Tl, T2, T3 is transmitted to the internal circuitry, it is clear that the input is some type of command signal. Thus, the input corresponds to the "command signal" [0034]) ;
Yoshii does not specifically disclose, a first input circuit configured to decode an enable signal for enabling the electronic circuit in an operating state, and output a decoded enable signal to the functional circuit; a test signal generator configured to generate a trigger signal for a test signal based on a signal change included in the command signal; and an arithmetic element configured to execute an operation of a negative OR of the decoded enable signal and the trigger signal, and output a signal of an operation result to the test circuit as a test signal for instructing execution of the test.
However, Yoshii teaches, [0057-0080], & [Fig.2] a configuration that does not add new functionality to the configuration shown in Fig. 1 and in which two terminals, namely, a dual-purpose external terminal CE and a dual-purpose external terminal Vout, are used instead of the dual-purpose external terminals T1, T2, T3 in the configuration shown in Fig. 1. Yoshii also indicates that [0019] an external terminal may be a chip enable (CE) terminal for selecting the operation/non-operation of the semiconductor device. This chip enable (CE) terminal is considered to refer to the dual-purpose external terminal CE shown in fig. 2, and document l is considered to indicate that the dual-purpose external terminal CE may be a chip enable terminal.
Therefore, the dual-purpose external terminals T1, T2, T3 in fig. l and the dual-purpose external terminal CE and dual-purpose external terminal Vout in Fig. 2 have the same function of switching to the test operation mode, and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove the dual-purpose external terminal T3 and the input from the same to the NAND circuit 12 as in the circuit in fig. 2 such that the two dual-purpose external terminals Tl, T2 remain and make T2 out of T1 and T2 a chip enable terminal in the circuit in Fig. 1.
The chip enable signal input into the chip enable terminal T2 is for selecting the operation/non-operation of the semiconductor and therefore corresponds to the "enable signal for bringing the electronic circuit into an operation state." The NMOS transistor M17 and PMOS transistor M13 of the switching circuit 10 generate a high or low signal in accordance with the input of the chip enable signal and determine whether to switch to the test mode and therefore decode the chip enable signal and correspond to the "first input circuit". The generated signal corresponds to the "decoded enable signal".
The NMOS transistor M16 and PMOS transistor M12 of the switching circuit 10 generate a high or low signal on the basis of the voltage input into the dual-purpose external terminal T1, generate a switching signal TS for switching to the test mode, and therefore correspond to the "test signal generator". The generated signal corresponds to the "trigger signal".
The NOR circuits 13, 14 of the switching circuit 10, which are logical operation elements, perform a NOR operation on the high or low signal from the dual-purpose external terminal T1 and the high or low signal from the chip enable terminal T2 and cause a switching signal TS for switching to the test mode to be generated on the basis of the signal of the operation result.
By doing so, Yosii’s circuit can perform a test operation without increasing the number of pins while preventing a malfunction that is erroneously switched to a test operation mode due to noise or the like [0012].
Regarding claim 4, Yoshii teaches, the electronic circuit as claimed in claim 3, further comprising a delay circuit inserted between the test signal generator and the arithmetic element, the delay circuit configured to delay the trigger signal by a processing time of the first input circuit, and output the delayed trigger signal to the arithmetic element (Yoshii: ‘providing a delay circuit 11 between the output side of the dual-purpose external terminal T1 and the NAND circuit 12, and providing such a delay circuit is a well-known feature for a person ordinary skill in the art’ [0041] & [Figs. 1-2]).
Regarding claim 5, Yoshii teaches, an electronic circuit comprising a functional circuit having a predetermined function (Yoshii: ‘the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "functional circuit" [0034]), and a test circuit that tests the functional circuit for debugging of the functional circuit (Yoshii: ‘performs test operation in the test operation mode’ [0034]), the electronic circuit comprising:
a second input circuit configured to decode a predetermined first command signal, and output the first decoded command signal to the functional circuit (Yoshii: ‘the dual-purpose external terminals T1, T2, T3 are used in the normal operation mode and are connected to the internal circuitry. Therefore, the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "second input circuit'' and the "functional circuit. Because the input to the dual-purpose external terminals Tl, T2, T3 is transmitted to the internal circuitry, it is clear that the input is some type of command signal. Thus, the input corresponds to the "command signal" [0034]);
Yoshii does not explicitly disclose, a first input circuit configured to decode an enable signal enabling the electronic circuit in an operating state, and output a decoded enable signal to the functional circuit; a first test signal generator configured to generate a first trigger signal for a test signal based on a signal change included in the first command signal; a third input circuit configured to decode a predetermined second command signal, and output the second decoded command signal to the functional circuit; a second test signal generator configured to generate a second trigger signal for a test signal based on a signal change included in the second command signal; and an arithmetic element configured to execute an operation of a negative OR of the decoded enable signal, the first trigger signal, and the second trigger signal, and output a signal of an operation result to the test circuit as a test signal for instructing execution of the test.
However, Yoshii teaches, [0001-0003, 0019, 0033-0080] & [Figs. 1-2] a configuration that does not add new functionality to the configuration shown in Fig. 1 and in which two terminals, namely, a dual-purpose external terminal CE and a dual-purpose external terminal Vout, are used instead of the dual-purpose external terminals T1, T2, T3 in the configuration shown in Fig. 1. Yoshii also indicates that [0019] an external terminal may be a chip enable (CE) terminal for selecting the operation/non-operation of the semiconductor device. This chip enable (CE) terminal is considered to refer to the dual-purpose external terminal CE shown in fig. 2, and document l is considered to indicate that the dual-purpose external terminal CE may be a chip enable terminal.
Therefore, the dual-purpose external terminals T1, T2, T3 in Fig. l and the dual-purpose external terminal CE and dual-purpose external terminal Vout in Fig. 2 have the same function of switching to the test operation mode, and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make T2 from among the dual-purpose external terminals T1, T2, and T3 in the circuit in fig. l a chip enable terminal, as in the circuit in Fig. 2.
The chip enable signal input into the chip enable terminal T2 is for selecting the operation/non-operation of the semiconductor and therefore corresponds to the "enable signal for bringing the electronic circuit into an operation state". The NMOS transistor M17 and PMOS transistor M13 of the switching circuit 10 generate a high or low signal in accordance with the input of the chip enable signal and determine whether to switch to the test mode and therefore decode the chip enable signal and correspond to the "first input circuit". The generated signal corresponds to the "decoded enable signal".
The NMOS transistor M16 and PMOS transistor M12 of the switching circuit 10 generate a high or low signal on the basis of the voltage input into the dual-purpose external terminal T1, generate a switching signal TS for switching to the test mode, and therefore correspond to the "test signal generator". The generated signal corresponds to the "trigger signal".
The NOR circuits 13, 14 of the switching circuit 10, which are logical operation elements, perform a NOR operation on the high or low signal from the dual-purpose external terminal T1 and the high or low signal from the chip enable terminal T2 and cause a switching signal TS for switching to the test mode to be generated on the basis of the signal of the operation result.
By doing so, Yosii’s circuit can perform a test operation without increasing the number of pins while preventing a malfunction that is erroneously switched to a test operation mode due to noise or the like [0012].
Regarding claim 6, Yoshii teaches, the electronic circuit as claimed in claim 5, further comprising: a first delay circuit inserted between the first test signal generator and the arithmetic element, the first delay circuit configured to delay the first trigger signal by a processing time of the first input circuit, and output a delayed first trigger signal to the arithmetic element; and a second delay circuit inserted between the second test signal generator and the arithmetic element, the second delay circuit configured to delay the second trigger signal by a processing time of the first input circuit, and output a delayed second trigger signal to the arithmetic element (Yoshii: ‘providing a delay circuit 11 between the output side of the dual-purpose external terminal T1 and the NAND circuit 12, and providing such a delay circuit is a well-known feature for a person ordinary skill in the art’ [0041] & [Figs. 1-2]).
Regarding claim 12, Yoshii teaches, a method of testing an electronic circuit, the electronic circuit comprising a functional circuit having a predetermined function (Yoshii: ‘the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "functional circuit" [0034]), and a test circuit that tests the functional circuit for debugging of the functional circuit (Yoshii: ‘performs test operation in the test operation mode’ [0034]), the method comprising the steps of:
decoding, by a second input circuit, a predetermined command signal and outputting the decoded command signal to the functional circuit (Yoshii: ‘the dual-purpose external terminals T1, T2, T3 are used in the normal operation mode and are connected to the internal circuitry. Therefore, the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "second input circuit'' and the "functional circuit. Because the input to the dual-purpose external terminals Tl, T2, T3 is transmitted to the internal circuitry, it is clear that the input is some type of command signal. Thus, the input corresponds to the "command signal" [0034]);
Yoshii does not specifically disclose, decoding, by a first input circuit, an enable signal for enabling the electronic circuit in an operating state, and outputting the decoded enable signal to the functional circuit; generating, by a test signal generator, a trigger signal for a test signal based on a signal change included in the command signal; and performing, by an arithmetic element, an operation of a negative OR of the decoded enable signal and the trigger signal, and outputting a signal of an operation result to the test circuit as a test signal for instructing execution of the test.
However, Yoshii teaches, [0057-0080], & [Fig.2] a configuration that does not add new functionality to the configuration shown in Fig. 1 and in which two terminals, namely, a dual-purpose external terminal CE and a dual-purpose external terminal Vout, are used instead of the dual-purpose external terminals T1, T2, T3 in the configuration shown in Fig. 1. Yoshii also indicates that [0019] an external terminal may be a chip enable (CE) terminal for selecting the operation/non-operation of the semiconductor device. This chip enable (CE) terminal is considered to refer to the dual-purpose external terminal CE shown in fig. 2, and document l is considered to indicate that the dual-purpose external terminal CE may be a chip enable terminal.
Therefore, the dual-purpose external terminals T1, T2, T3 in fig. l and the dual-purpose external terminal CE and dual-purpose external terminal Vout in Fig. 2 have the same function of switching to the test operation mode, and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove the dual-purpose external terminal T3 and the input from the same to the NAND circuit 12 as in the circuit in fig. 2 such that the two dual-purpose external terminals Tl, T2 remain and make T2 out of T1 and T2 a chip enable terminal in the circuit in Fig. 1.
The chip enable signal input into the chip enable terminal T2 is for selecting the operation/non-operation of the semiconductor and therefore corresponds to the "enable signal for bringing the electronic circuit into an operation state." The NMOS transistor M17 and PMOS transistor M13 of the switching circuit 10 generate a high or low signal in accordance with the input of the chip enable signal and determine whether to switch to the test mode and therefore decode the chip enable signal and correspond to the "first input circuit". The generated signal corresponds to the "decoded enable signal".
The NMOS transistor M16 and PMOS transistor M12 of the switching circuit 10 generate a high or low signal on the basis of the voltage input into the dual-purpose external terminal T1, generate a switching signal TS for switching to the test mode, and therefore correspond to the "test signal generator". The generated signal corresponds to the "trigger signal".
The NOR circuits 13, 14 of the switching circuit 10, which are logical operation elements, perform a NOR operation on the high or low signal from the dual-purpose external terminal T1 and the high or low signal from the chip enable terminal T2 and cause a switching signal TS for switching to the test mode to be generated on the basis of the signal of the operation result.
By doing so, Yosii’s circuit can perform a test operation without increasing the number of pins while preventing a malfunction that is erroneously switched to a test operation mode due to noise or the like [0012].
Regarding claim 13, Yoshii teaches, a method of testing an electronic circuit, the electronic circuit comprising a functional circuit having a predetermined function(Yoshii: ‘the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "functional circuit" [0034]), and a test circuit that tests the functional circuit for debugging of the functional circuit (Yoshii: ‘performs test operation in the test operation mode’ [0034]), the method comprising the steps of:
decoding, by a second input circuit, a predetermined first command signal, and outputting the first decoded command signal to the functional circuit (Yoshii: ‘the dual-purpose external terminals T1, T2, T3 are used in the normal operation mode and are connected to the internal circuitry. Therefore, the internal circuitry connected to the dual-purpose external terminals T1, T2, T3 corresponds to the "second input circuit'' and the "functional circuit. Because the input to the dual-purpose external terminals Tl, T2, T3 is transmitted to the internal circuitry, it is clear that the input is some type of command signal. Thus, the input corresponds to the "command signal" [0034]);
Yoshii does not explicitly disclose, decoding, by a first input circuit, an enable signal for enabling the electronic circuit in an operating state, and outputting the decoded enable signal to the functional circuit; generating, by a first test signal generator, a first trigger signal for a test signal based on a signal change included in the first command signal; decoding, by a third input circuit, a predetermined second command signal, and outputting the second decoded command signal to the functional circuit; generating, by a second test signal generator, a second trigger signal for a test signal based on a signal change included in the second command signal; and performing, by an arithmetic element, an operation of a negative OR of the decoded enable signal, the first trigger signal, and the second trigger signal, and outputting a signal of an operation result to the test circuit as a test signal for instructing execution of the test.
However, Yoshii teaches, [0001-0003, 0019, 0033-0080] & [Figs. 1-2] a configuration that does not add new functionality to the configuration shown in Fig. 1 and in which two terminals, namely, a dual-purpose external terminal CE and a dual-purpose external terminal Vout, are used instead of the dual-purpose external terminals T1, T2, T3 in the configuration shown in Fig. 1. Yoshii also indicates that [0019] an external terminal may be a chip enable (CE) terminal for selecting the operation/non-operation of the semiconductor device. This chip enable (CE) terminal is considered to refer to the dual-purpose external terminal CE shown in fig. 2, and document l is considered to indicate that the dual-purpose external terminal CE may be a chip enable terminal.
Therefore, the dual-purpose external terminals T1, T2, T3 in Fig. l and the dual-purpose external terminal CE and dual-purpose external terminal Vout in Fig. 2 have the same function of switching to the test operation mode, and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make T2 from among the dual-purpose external terminals T1, T2, and T3 in the circuit in fig. l a chip enable terminal, as in the circuit in Fig. 2.
The chip enable signal input into the chip enable terminal T2 is for selecting the operation/non-operation of the semiconductor and therefore corresponds to the "enable signal for bringing the electronic circuit into an operation state". The NMOS transistor M17 and PMOS transistor M13 of the switching circuit 10 generate a high or low signal in accordance with the input of the chip enable signal and determine whether to switch to the test mode and therefore decode the chip enable signal and correspond to the "first input circuit". The generated signal corresponds to the "decoded enable signal".
The NMOS transistor M16 and PMOS transistor M12 of the switching circuit 10 generate a high or low signal on the basis of the voltage input into the dual-purpose external terminal T1, generate a switching signal TS for switching to the test mode, and therefore correspond to the "test signal generator". The generated signal corresponds to the "trigger signal".
The NOR circuits 13, 14 of the switching circuit 10, which are logical operation elements, perform a NOR operation on the high or low signal from the dual-purpose external terminal T1 and the high or low signal from the chip enable terminal T2 and cause a switching signal TS for switching to the test mode to be generated on the basis of the signal of the operation result.
By doing so, Yosii’s circuit can perform a test operation without increasing the number of pins while preventing a malfunction that is erroneously switched to a test operation mode due to noise or the like [0012].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshii et el. (JP 2011066473 A) in view of Noguchi (US 2002/0017688 A1), (hereinafter Yoshii-Noguchi).
Regarding claim 7, Yoshii does not explicitly disclose, the electronic circuit as claimed in claim 3, wherein the test signal generator comprises: a series circuit including a resistor and a gate-grounded MOS transistor which are connected in series, the series circuit being connected between a predetermined power supply voltage and an input terminal of the command signal; and an inverter configured to invert a signal from an output terminal of the MOS transistor, and output the inverted signal as the trigger signal.
However, Noguchi teaches in an analogous art, [0006-0008] & [Fig. 12] voltage detection for shifting to a test mode in which provided are a series circuit comprising a resistor 3 and gate-grounded NMOS transistors 2-1 to 2-n that are connected in series between a ground point and a terminal 1 that is an input point and an inverter 4 that inverts the signal from the NMOS transistors, and the test mode is shifted to when a voltage equal to or greater than a prescribed voltage is applied. Such a voltage detection feature is a well-known feature, and the ground point is used as a reference point for a prescribed potential.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a power supply having a prescribed potential instead of the ground point and shift to the test mode when the input voltage is lower than the prescribed voltage.
By doing so, instead of the configuration in which a voltage equal to or greater than a threshold voltage is detected by the NMOS transistors and PMOS transistors, a person skilled in the art could easily have adopted a voltage detection circuit that, uses a resistor, gate-grounded MOS transistors, and an inverter.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshii et el. (JP 2011066473 A) in view of Mizoguchi (US 2014/0197841 A1), and further in view of Ooishi (US 2004/0085845 A1), (hereinafter Yoshii-Mizoguchi-Ooishi).
Regarding claim 8, Yoshii does not explicitly disclose, the electronic circuit as claimed in claim 3, wherein the test signal generator comprises: a DC voltage source configured to apply a predetermined offset voltage to a signal which is input to an input terminal of the command signal; and a comparator configured to compare the signal to which the offset voltage is applied with a power supply voltage or a ground voltage, and output a comparison result signal as the trigger signal.
However, Mizoguchi teaches in an analogous art, [0037-0038] an offset power supply circuit 70 adding a prescribed offset voltage, and adjusting voltage using such an offset power supply is a well-known feature. Furthermore, using a comparator for comparison with a prescribed potential is a well-known feature, as indicated by Ooishi ([0074-0077] & [Fig. 4]).
The invention disclosed in Yoshii, instead of the configuration in which a voltage equal to or greater than a threshold voltage is detected by the NMOS transistors and PMOS transistors, a person skilled in the art before the effective filing date of the claimed invention could easily have adopted the well-known features described in Mizoguchi and Ooishi, provided an offset power supply that adds a prescribed offset voltage to the input from the terminal, and used a comparator for comparison with a prescribed potential.
Claim 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshii et el. (JP 2011066473 A) in view of Ooishi (US 2004/0085845 A1), (hereinafter Yoshii- Ooishi).
Regarding claim 9, Yoshii does not explicitly disclose, the electronic circuit as claimed in claim 3, wherein the test signal generator comprises: a voltage-dividing resistor configured to divide a voltage of a signal which is input to an input terminal of the command signal, and output a divided voltage; and a comparator configured to compare the divided voltage with a power supply voltage, and output a comparison result signal as the trigger signal.
However, the feature of using voltage dividing resistor to divide an input voltage and the feature of using a comparator to compare the divided voltages are well known, as indicated by Ooishi ([0074-0077] & [Fig. 4]).
The invention disclosed in Yoshii, instead of the configuration in which a voltage equal to or greater than a threshold voltage is detected by the NMOS transistors and PMOS transistors, a person ordinary skill in the art before the effective filing date of the claimed invention could easily have adopted the well-known features described by Ooishi and compared a voltage obtained by dividing the input from the terminal with a prescribed voltage or with a divided prescribed voltage.
Regarding claim 10, Yoshii-Ooishi teaches, the electronic circuit as claimed in claim 3, wherein the test signal generator comprises: a first voltage-dividing resistor configured to divide a voltage of a power supply voltage, and outputs a first divided voltage; a second voltage-dividing resistor configured to divide a voltage of a signal input to an input terminal of the command signal, and output a second divided voltage; and a comparator configured to compare the first divided voltage with the second divided voltage, and output a comparison result signal as the trigger signal (Ooishi ([0074-0077] & [Fig. 4]).
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Li (US 2023/0197179 A1) teaches a test circuit. The circuit includes: an input terminal, a processing circuit, and an output terminal. The input terminal receives an input signal. The input signal includes a test command for indicating a test target circuit module and an address of the target circuit module. The processing circuit responds to the test command and the target. The address of the circuit module determines the test mode signal, the test mode signal carries the test type, the test mode signal is used to trigger the target circuit module to perform the test corresponding to the test type, and the output terminal sends the test mode signal to the target circuit module according to the address of the target circuit module. Thus, the test mode signal can be accurately transmitted to different circuit modules in the memory chip.
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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