DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of national stage of a 371 of international application PCT/CN2023/135629 filed on 11/30/2023 is acknowledged.
Preliminary Amendment
The preliminary amendment filed on 10/30/2024 was entered and claim 10 cancelled, claims 1-9, 11-21 examined.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because FIG. 4 middle section is illegible, especially for the part inside pointers table submodule 132. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2-6, 11-15, 17-21 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 2, 11, 17 recite limitation “the controller is configured for determining whether a second memory of a thread corresponding to the to-be-stored instruction is idle; the controller is configured for storing the to-be-stored instruction in the first memory when the second memory is not idle; the controller is further configured for storing the to-be-stored instruction in the second memory when the second memory of the thread corresponding to the to-be-stored instruction is idle; and the controller is further configured for outputting the instruction of the thread in the first memory, corresponding to the second memory, to the second memory when any one of the second memories is idle.”
It would have been unclear to a person of ordinary skill in the art the metes and bounds of the limitations related to idle and not idle. For example, the recitation of “idle” in the limitations means the thread is idle/inactive OR a second memory, corresponding to a thread, is idle/inactive? Does the limitation “the second memory is not idle” mean the second memory has no more space/room for storing instructions of a thread?
For the purpose of examination, the office interprets “the second memory is not idle” as the second memory has no more memory space for storing instructions of a thread and “the second memories is idle” as the second memory has memory space for storing instructions for a thread.
Claim 3-6, 12-15, 18-21 inherit the rejection from claim 2, 11, 17, respectively.
Claim 5, 14, 20 recite the limitation ““wherein the multi-threaded storage unit further comprises a scheduler, connected to the first memory and the chain buffer status table module, and the scheduler is configured for scheduling an output of an instruction from a second memory;”
Claim recites “a scheduler, connect to the first memory”. However, FIG. 4 shows
scheduler 150 is connected to second memories 140. Scheduler 150 is not connected to first memory 110.
Further, claim recites “the scheduler is configured for scheduling an output of an
instruction from a second memory”. Therefore, the second memory is where the instructions are outputted to the scheduler, and the second memory and the scheduler should be connected.
Clarification/correction is needed.
Allowable Subject Matter
Claim 2-6, 11-15, 17-21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Also, the allowance is contingent on overcoming 112 (b) rejections.
REASONS FOR ALLOWANCE
For claim 2, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 2 depends.
For claim 3, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 3 depends. Additionally, claim 3 is allowable based on dependency from claim 2.
For claim 4, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 4 depends. Additionally, claim 4 is allowable based on dependency from claim 3.
For claim 5, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 5 depends. Additionally, claim 5 is allowable based on dependency from claim 3.
For claim 6, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 6 depends. Additionally, claim 6 is allowable based on dependency from claim 3.
For claim 11, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 11 depends.
For claim 12, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 12 depends. Additionally, claim 12 is allowable based on dependency from claim 11.
For claim 13, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 13 depends. Additionally, claim 13 is allowable based on dependency from claim 12.
For claim 14, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 14 depends. Additionally, claim 14 is allowable based on dependency from claim 12.
For claim 15, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 15 depends. Additionally, claim 15 is allowable based on dependency from claim 12.
For claim 17, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 17 depends.
For claim 18, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 18 depends. Additionally, claim 18 is allowable based on dependency from claim 17.
For claim 19, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 19 depends. Additionally, claim 19 is allowable based on dependency from claim 18.
For claim 20, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 20 depends. Additionally, claim 20 is allowable based on dependency from claim 18.
For claim 21, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 21 depends. Additionally, claim 21 is allowable based on dependency from claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-9, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Barreh (US 20120233441), in view of Cui (US 20250123845), further in view of Luttrell (US 20100299508).
Regarding Claim 1, Barreh teaches
A multi-threaded storage unit, comprising: (Barreh [0001] the use of instruction buffers in a multi-threaded environment.) a first memory, configured for storing instructions corresponding to different threads as a data field of a chain table; (Barreh [0033] in FIG. 1, instruction buffer 100 comprises a memory array 110 that includes a plurality of entries 120. Thus, in the embodiment of FIG. 1, an entry 120 exists at each row location for each one of threads 0-3) (i.e., instruction buffer 100 is a first memory, memory array 110 is a table)
a controller, connected to the first memory, wherein the controller is configured for receiving a to-be-stored instruction and storing the to-be-stored instruction into the first memory; (Barreh [0031] instructions (and other accompanying information such as predecode bits and instruction addresses) may arrive at instruction buffer 100 via a first bus 140. Similarly, outgoing instructions may be sent via a second bus 140. Each bus 140 may be configured the same or configured differently, and includes suitable wiring, circuitry, and/or accompanying control logic as would be known to one with skill in the art in order to facilitate transport of instructions (and other data) into out and out of instruction buffer 100.)
and a chain buffer status table module, connected to the first memory and configured for generating a storage record of the to-be-stored instruction in the first memory in response to a storage of the to-be-stored instruction in the first memory, (Barreh [0029] Instruction fetch unit 180, from which instruction buffer 100 is configured to receive instructions, may have any number of configurations in various embodiments, as would occur to those with skill in the art of processor design. [0036] Entries 120 in memory array 110 may be accessed using a set of control information 150… within an instruction buffer to store one or more instructions arriving at an instruction buffer, and subsequently updating the indicator to be reflective of the changed status of the memory array(s).) (i.e., instruction fetch unit 180 is a buffer status table module)
wherein the storage record comprises an address of the to-be-stored instruction in the first memory, (Barreh [0031] instructions (and other accompanying information such as predecode bits and instruction addresses) may arrive at instruction buffer 100)
Barreh teaches ([0002]) pass instructions down a pipeline but Barreh does not explicitly teach to-be-stored instruction
However, Cui teaches to-be-stored instruction (Cui [0037] Instructions are stored in the instruction cache [0041] There are usually buffer queues between the functional units of the SMT2 processor (i.e., the branch prediction unit, the instruction cache, the decoder group, and the micro-op dispatch). From front to back, there are instruction fetching request queue, instruction queue, and micro-op queue.) (i.e., instruction cache is before dispatch/issue/scheduling stage in the processor pipeline. At dispatch/issue/scheduling stage, instructions are stored for execution of instruction. Therefore, instructions in the instruction cache, before the instructions reach the scheduler, are to-be-stored instructions)
Barreh and Cui are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Barreh and Cui to modify Barreh‘s instruction buffer with Cui’s teaching of instruction buffer is used before dispatch/schedule stage. The motivation for doing so would be to (Cui [0005]) improve the efficiency of the simultaneously multi-threading processor.
Barreh-Cui does not teach a chain table, and the address is configured for representing a pointer field of a node in the chain table.
However, Luttrell teaches chain table (Luttrell [0068] utilize a linked list method to maintain ordering of store instructions) (i.e., linked list is chain table)
and the address is configured for representing a pointer field of a node in the chain table. (Luttrell [0070] The address array entries 412 may be dynamically allocated by tag generation logic, an address, and a prior link pointer value)
Barreh, Cui and Luttrell are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Barreh, Cui and Luttrell to modify Barreh- Cui‘s instruction buffer with Luttrell’s teaching of a linked list as chain table. The motivation for doing so would be to (Luttrell [0068]) utilize a linked list method to maintain ordering of store instructions.
Regarding Claim 7, Barreh, Cui and Luttrell teach
Barreh teaches wherein the to-be-stored instruction is inserted into a predetermined position in the chain buffer in a form of a node [entry] of the chain table; (Barreh [0004] instructions received at an instruction buffer can be stored at any entry within a memory array.)
and the chain buffer status table module is configured for obtaining a first address of a corresponding [entry] node of the to-be-stored instruction in the first memory and a second address of a node following the predetermined position; (Barreh [0029] Instruction fetch unit 180, from which instruction buffer 100 is configured to receive instructions [0031] instructions (and other accompanying information such as instruction addresses) may arrive at instruction buffer 100. [0033] instruction buffer 100 comprises a memory array 110 that includes a plurality of entries 120) (i.e., instruction fetch unit is the buffer status table module that obtains instructions and puts them into instruction buffer which in turn holds the instruction information in a memory array, each entry of a memory array/table has instruction address, first entry with first address and second entry with second address)
Barreh does not teach but Cui teaches to-be-stored instruction (Cui [0037] Instructions are stored in the instruction cache [0041] There are usually buffer queues between the functional units of the SMT2 processor (i.e., the branch prediction unit, the instruction cache, the decoder group, and the micro-op dispatch). From front to back, there are instruction fetching request queue, instruction queue, and micro-op queue.) (i.e., instruction cache is before dispatch/issue/scheduling stage in the processor pipeline. At dispatch/issue/scheduling stage, instructions are stored for execution of instruction. Therefore, instructions in the instruction cache are to-be-stored instructions)
Barreh and Cui are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Barreh and Cui to modify Barreh‘s instruction buffer with Cui’s teaching of instruction buffer is used before dispatch/schedule stage. The motivation for doing so would be to improve the efficiency of the simultaneously multi-threading processor(Cui [0005]).
Barreh-Cui does not teach but Luttrell teaches a predetermined position in a node of the chain table (Luttrel [0068] The prior link field 428 may utilize a linked list method to maintain ordering of store instructions within a thread by being configured to hold a pointer value to the last store queue entry allocated for the corresponding thread. [0073] The prior link field 428 may be used to manage the relative ordering of all store instruction [0075] This head pointer register may hold an identifier value of a store queue entry holding the first store instruction of a chain of committed store instructions of the particular thread) (i.e. the head pointer register holds an value for storing first instruction of a thread into a queue, so the head/first position is the predetermined position, each queue entry in the linked list is a node of the chain table,)
a node following the predetermined position; (Luttrel [0068] The pointer value buffered in the prior link field 428 points from the current store instruction corresponding to the current entry to an immediate prior store that was previously allocated.)
updating a pointer field of a node preceding the predetermined position to the first address; (Luttrel [0069] Address Array Entries, Address Prior Link [0076] the chain of committed store instructions is updated with the current committed store instruction.)
and updating a pointer field of a node corresponding to the predetermined position to the second address. (Luttrel [0069] Address Array Entries, Address Prior Link [0076] the chain of committed store instructions is updated with the current committed store instruction.)
Barreh, Cui and Luttrell are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Barreh, Cui and Luttrell to modify Barreh- Cui‘s instruction buffer with Luttrell’s teaching of a linked list as chain table. The motivation for doing so would be to (Luttrell [0068]) utilize a linked list method to maintain ordering of store instructions.
Regarding Claim 8, Barreh, Cui and Luttrell teach
A chip, comprising the multi-threaded storage unit according to claim 1. (Barreh [0004] by storing instructions for a plurality of threads in one or more memory arrays, a reduced number of hardware structures and/or amount of chip space may be used to implement an instruction buffer.)
Regarding Claim 9, Barreh, Cui and Luttrell teach
An electronic device, comprising the chip according to claim 8. (Barreh [0023] "configured to" may include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.)
Regarding Claim 16, Barreh, Cui and Luttrell teach
Barreh teaches wherein the to-be-stored instruction is inserted into a predetermined position in the chain buffer in a form of a node [entry] of the chain table; (Barreh [0004] instructions received at an instruction buffer can be stored at any entry within a memory array.)
and the chain buffer status table module is configured for obtaining a first address of a corresponding [entry] node of the to-be-stored instruction in the first memory and a second address of a node following the predetermined position; (Barreh [0029] Instruction fetch unit 180, from which instruction buffer 100 is configured to receive instructions [0031] instructions (and other accompanying information such as instruction addresses) may arrive at instruction buffer 100. [0033] instruction buffer 100 comprises a memory array 110 that includes a plurality of entries 120) (i.e., instruction fetch unit is the buffer status table module that obtains instructions and puts them into instruction buffer which in turn holds the instruction information in a memory array, each entry of a memory array/table has instruction address, first entry with first address and second entry with second address)
Barreh does not teach but Cui teaches to-be-stored instruction (Cui [0037] Instructions are stored in the instruction cache [0041] There are usually buffer queues between the functional units of the SMT2 processor (i.e., the branch prediction unit, the instruction cache, the decoder group, and the micro-op dispatch). From front to back, there are instruction fetching request queue, instruction queue, and micro-op queue.) (i.e., instruction cache is before dispatch/issue/scheduling stage in the processor pipeline. At dispatch/issue/scheduling stage, instructions are stored for execution of instruction. Therefore, instructions in the instruction cache are to-be-stored instructions)
Barreh and Cui are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Barreh and Cui to modify Barreh‘s instruction buffer with Cui’s teaching of instruction buffer is used before dispatch/schedule stage. The motivation for doing so would be to improve the efficiency of the simultaneously multi-threading processor (Cui [0005]).
Barreh-Cui does not teach but Luttrell teaches a predetermined position in a node of the chain table (Luttrel [0068] The prior link field 428 may utilize a linked list method to maintain ordering of store instructions within a thread by being configured to hold a pointer value to the last store queue entry allocated for the corresponding thread. [0073] The prior link field 428 may be used to manage the relative ordering of all store instruction [0075] This head pointer register may hold an identifier value of a store queue entry holding the first store instruction of a chain of committed store instructions of the particular thread) (i.e. the head pointer register holds an value for storing first instruction of a thread into a queue, so the head/first position is the predetermined position, each queue entry in the linked list is a node of the chain table,)
a node following the predetermined position; (Luttrel [0068] The pointer value buffered in the prior link field 428 points from the current store instruction corresponding to the current entry to an immediate prior store that was previously allocated.)
updating a pointer field of a node preceding the predetermined position to the first address; (Luttrel [0069] Address Array Entries, Address Prior Link [0076] the chain of committed store instructions is updated with the current committed store instruction.)
and updating a pointer field of a node corresponding to the predetermined position to the second address. (Luttrel [0069] Address Array Entries, Address Prior Link [0076] the chain of committed store instructions is updated with the current committed store instruction.)
Barreh, Cui and Luttrell are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Barreh, Cui and Luttrell to modify Barreh- Cui‘s instruction buffer with Luttrell’s teaching of a linked list as chain table. The motivation for doing so would be to (Luttrell [0068]) utilize a linked list method to maintain ordering of store instructions.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Barreh (US 7185178) teaches fetch speculation in a multithreaded processor having a condition when instruction buffer does not have enough room to store the fetched instructions.
Conclusion
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/WEI MA/Examiner, Art Unit 2135
